Team,
Can you please help customer address below inquiry (Thanks):
We are working on the mobile DDR interface and I have a few questions. First, the interface appears to work with the 133MHz mDDR setup in a gel file that Rich has. We are trying to get it to work at 171MHz max rate which we need for our thruput. We have 200MHz Micron parts on the board MT46H64M16LFCK-5L_IT. Following SPRUEH7D which describes the Memory Controller for the mDDR/DDR2, I altered the following registers: PLL2CTRL, DDRPHYCTL1, SDCR,SDCR2,SDTIMR,SDTIMR2 and SDRCR. After altering these registers, the memory tests no longer passes, but I did see the clock running at 171MHz from the memory controller. On the descriptions of these registers some parameters do not seem to be directly applicable to the Micron mDDR that we are using, so here are the questions:
1) SDTIMR2 uses timing parameters tXSNR and tXSRD which the MT46H64M16LFCK-5L_IT does not have. It does have tXSR which is “Exit self refresh to first valid command”, so I used this parameter for both tXSNR and XSRD??
2) tRTP, also, is not in the Micron data sheets.
3) tCKE = 1, equation says to use value tCKE -1 which would = 0, is this valid?
