Is there a way to connect the EMIFB to an ASYNCHRONOUS SRAM, instead of an SDRAM?
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Is there a way to connect the EMIFB to an ASYNCHRONOUS SRAM, instead of an SDRAM?
Jeff,
Attached is a block dagram of what we want to do. What would you recommend is the best way to connect a C674x DSP to a Xilinx Spartan-6 FPGA?
Traian/Ray:
On 6748 you can use Upp. On 6747 you can use EMIFB to interface to FPGA.
Xilinx has an app note to interface older processors (671x, 64x) to EMIF
http://www.xilinx.com/support/documentation/application_notes/xapp753.pdf
Question for factory experts..
Are there any gotchas using this reference with a 674x EMIFB ?. Is there a newer FPGA-EMIF connection collateral available ?
Thanks,
Pradhyum
Pradhyum,
If possible, I would recommend using EMIFA asynch mode to interface with the FPGA. The SDRAM interface is a lot more difficult to handle.
This was a discussion on EMIFA-SDRAM mode to FPGA which turned into a fairly confusing debug effort. The lessons learned on EMIFA-SDRAM may not apply directly to EMIFB-SDRAM: http://e2e.ti.com/support/arm174_microprocessors/omap_applications_processors/f/42/p/34528/120224.aspx#120224
-Tommy