McASP Transmitter AXR is dead

Sherry Ismail

Other Parts Discussed in Thread: OMAPL138, TLV320AIC3106

My goal is to achieve Stereo Audio echo. Before echo, I want to see if AXR7 pin (a serialiser used as a TX) even transmits or not..

I followed instructions for McASP initialisation and starting up module from C6000 peripheral guide.pdf. It works for polling but not for Interrupt. Here is the problem:
When I use polling, the AXR7 line on LCDKc6748 ( pin #28 on J15 pin header) transmits data on each slot (slot 0 &1 for 2-slot TDM, I2S protocol). But when I start BIOS and use the exact same code for Interrupt based system, TX line is dead. Underrun and XERR occur.

The initialisation and startup of polling and interrupt are exactly the same. The only difference is that in polling, I put the polling code inside a while(1) loop before BIOS_start() command. For McASP, I remove the while{1} loop and put the exact same code into I2S_ISR() which is called upon Hwi.

My code that works on polling is as follows

while (1)	// loop forever
	{
	if (mcaspRegs->XSTAT & 0x00000020)		// If Tx data ready flag is up
		{
		if (mcaspRegs->XSTAT & 0x00000040)	// start of frame
				{
			mcaspRegs->XBUF7 = 0x55555555;
			mcaspRegs->XSTAT = 0x00000040;	// clear the start of frame flag
		} else if (mcaspRegs->XSTAT & 0x00000010)// if it is last slot of frame
				{
			mcaspRegs->XBUF7 = 0x7FFFFFFF;
			mcaspRegs->XSTAT = 0x00000010;	// clear last slot flag
		}
		mcaspRegs->XSTAT |= 0x00000020;	// clear XDATA flag
		}
	}

Then I copy the same code into I2S_ISR() and in app.cfg, following settings on app.cfg

UART_ISR	Event # 69	CPU interrupt #5
I2S_ISR	Event #61	CPU interrupt #7

Also in McASP initialisation, I allow TX interrupt

mcaspRegs->XINTCTL = 0x00000020;

Even if I interchange the CPU interrupt so that McASP has a higher priority than UART and is uninterrupted (BTW UART for me works fine)..... still nothing on the TX line!!! the XBUFn shows the value that I have written on it in my code. Please see my project attached. It is located in C:\ti\WorkspaceI2S Master.rar

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

Thanks for your post.

I have reviewed your source code and it seems, you have not enabled the error interrupts through INTCTL. I would recommend you to setup the McASP error interrupts through DSP interrupt contoller and you could register the corresponding ISR with the CPU maskable interrupts through enabling the specified transmitter & receiver interrupts through API's McASPTxIntEnable & McASPRxIntEnable. The code snippet for the same is given below:

McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR

| MCASP_TX_CLKFAIL

| MCASP_TX_SYNCERROR

| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR

| MCASP_RX_CLKFAIL

| MCASP_RX_SYNCERROR

| MCASP_RX_OVERRUN);

void McASPTxIntEnable(unsigned int baseAddr, unsigned int intMask)

{

HWREG(baseAddr + MCASP_XINTCTL) |= intMask;

}

void McASPRxIntEnable(unsigned int baseAddr, unsigned int intMask)

{

HWREG(baseAddr + MCASP_RINTCTL) |= intMask;

}

For more details to configure the transmitter and receiver interrupt control registers (XINTCTL & RINTCTL), kindly refer sections 26.3.20 & 26.3.32 in the OMAPL137 TRM below:

http://www.ti.com/lit/ug/spruh92b/spruh92b.pdf

However, you could also try McASP echo rCSL DSP based example available for omapl138 EVM which has C6748 DSP core in it. You couldn't use the McASP Echo example directly, but however you would require platform level porting efforts to transfer the code from EVM and appropriately modify the h/w level code changes compatible to LCDK H/W platform.

The McASP Echo register rCSL examplewhich provides a non-OS based example without EDMA of how to use the C674x DSP in conjunction with the McASP to receive and transmit 24 bit audio data from the TLV320AIC3106 codec.

You could download the QuickStartOMAPL1x rCSL package from the below wiki

http://processors.wiki.ti.com/index.php/QuickStartOMAPL1x_rCSL#Downloads

From the above, please check the McASP Echo example synopsis from the below section:

http://processors.wiki.ti.com/index.php/QuickStartOMAPL1x_rCSL#Example_Synopsis

After installing QuickStartOMAPL1x rCSL package, you could see the McASP Echo audio example from the below specified path which is without using EDMA:

~\ti\quickStartOMAPL1x_rCSL\OMAPL1x\rCSL_examples\evmOMAPL138\DSP_examples\mcasp

Kindly read the McASPEcho_README.pdf document available from the above installation path.

Thanks & regards,

Sivaraj K

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0 Sherry Ismail over 9 years ago in reply to Sivaraj Kuppuraj

Intellectual 885 points

Thank you for your reply. My code is already influenced by rCSL example (you suggested this before).
I have enabled interrupt due to DMAERROR, CLKFAIL,SYNCERROR,OVERRUN/Underrun.

The underrun bit is set just after McASP_start() (because in the end of McASP_start(), the State machine of TX/RX is enabled and XDATA flag is set).
By the time my program starts BIOS and reaches I2S_ISR() due to interrupt, the under run bit is already set and my program goes into idle loop. WHat should I do to get McASP back to work after underrun bit is set. It suggests here to reset the module, processors.wiki.ti.com/.../McASP_Tips, but it does not make sense to restart McASP module within ISR.

0 Sherry Ismail over 9 years ago in reply to Sivaraj Kuppuraj

Intellectual 885 points

Sivaraj ! I am using BIOS. Do I still have to use functions like McASPTxIntEnable(), McASPRxIntEnable() etc???

I thought app.cfg binds CPU interrupt to I2S_ISR interrupts.

I have put the McASP startup function ( e.g. Activate serialisers, Enable State machine, Enable High Freq. clock, Bit clock and Frame Sync) Inside a Task called myTask. So after starting BIOS, in absence of HWI, SWI, semaphore etc, the BIOS executes myTask. When serialiser is activated, it causes interrupt, myTask is paused and XBUF is serviced inside ISR, before continuing.

After removing log_info0() I have no Underrun. But the TX line is still dead. Any suggestions please?

0 Sivaraj Kuppuraj over 9 years ago in reply to Sherry Ismail

TI__Mastermind 35645 points

Hi,

Please share your regiser dump while debugging the code when you see Tx. line is dead.

Thanks & regards,
Sivaraj K

0 Sherry Ismail over 9 years ago in reply to Sivaraj Kuppuraj

Intellectual 885 points

It started working after i changed the ISR conditions. I changed it to the following

if (mcaspRegs->XSTAT & 0x00000100)
	{
		Log_info1("TX underrun : [%x]", mcaspRegs->XSTAT);
		mcaspRegs->XSTAT = 0x00000101;
		while (mcaspRegs->XSTAT & 0x00000001)
			;
		while (mcaspRegs->XSTAT & 0x00000100)
			;
	}
else if ((mcaspRegs->XSTAT & 0x00000020))	//XBUF ready
	{
		if (mcaspRegs->XSTAT & 0x00000040)		//Start of frame
		{
			mcaspRegs->XBUF7 = sample_left;
			mcaspRegs->XSTAT = 0x00000040;
		}
		else
		{
			mcaspRegs->XBUF7 = sample_right;
			mcaspRegs->XSTAT = 0x00000010;
		}
		mcaspRegs->XSTAT = 0x00000020;
	}

Instead of using if (check start of frame bit) else if ( check Last slot bit) ;... I made it if ( check start of frame) ...and else.

0 Sherry Ismail over 9 years ago in reply to Sherry Ismail

Intellectual 885 points

Fullscreen 0285.register dump.txt Download

521177 103
R McASP0_REVID 0x0000000B 0x44300A02
R McASP0_PFUNC 0x0000000B 0x00000000
R McASP0_PDIR 0x0000000B 0xB6000080
R McASP0_PDOUT 0x0000000B 0x00000000
R McASP0_PDIN 0x0000000B 0x7E00BF6F
R McASP0_PDSET 0x0000000B 0x7A00BF4F
R McASP0_PDCLR 0x0000000B 0x00000000
R McASP0_GBLCTL 0x0000000B 0x00001F1E
R McASP0_AMUTE 0x0000000B 0x00000000
R McASP0_DLBCTL 0x0000000B 0x00000000
R McASP0_DITCTL 0x0000000B 0x00000000
R McASP0_RGBLCTL 0x0000000B 0x00001F1E
R McASP0_RMASK 0x0000000B 0xFFFFFFFF
R McASP0_RFMT 0x0000000B 0x000080F8
R McASP0_AFSRCTL 0x0000000B 0x00000112
R McASP0_ACLKRCTL 0x0000000B 0x001800A3
R McASP0_AHCLKRCTL 0x0000000B 0x00000000
R McASP0_RTDM 0x0000000B 0x00000003
R McASP0_RINTCTL 0x0000000B 0x00000020
R McASP0_RSTAT 0x0000000B 0x00000171
R McASP0_RSLOT 0x0000000B 0x00000001
R McASP0_RCLKCHK 0x0000000B 0x00FF0008
R McASP0_REVTCTL 0x0000000B 0x00000000
R McASP0_XGBLCTL 0x0000000B 0x00001F1E
R McASP0_XMASK 0x0000000B 0xFFFFFFFF
R McASP0_XFMT 0x0000000B 0x000080F8
R McASP0_AFSXCTL 0x0000000B 0x00000112
R McASP0_ACLKXCTL 0x0000000B 0x000000A3
R McASP0_AHCLKXCTL 0x0000000B 0x00000000
R McASP0_XTDM 0x0000000B 0x00000003
R McASP0_XINTCTL 0x0000000B 0x00000020
R McASP0_XSTAT 0x0000000B 0x00000171
R McASP0_XSLOT 0x0000000B 0x00000001
R McASP0_XCLKCHK 0x0000000B 0x00FF0008
R McASP0_XEVTCTL 0x0000000B 0x00000000
R McASP0_DITCSRA0 0x0000000B 0x00000000
R McASP0_DITCSRA1 0x0000000B 0x00000000
R McASP0_DITCSRA2 0x0000000B 0x00000000
R McASP0_DITCSRA3 0x0000000B 0x00000000
R McASP0_DITCSRA4 0x0000000B 0x00000000
R McASP0_DITCSRA5 0x0000000B 0x00000000
R McASP0_DITCSRB0 0x0000000B 0x00000000
R McASP0_DITCSRB1 0x0000000B 0x00000000
R McASP0_DITCSRB2 0x0000000B 0x00000000
R McASP0_DITCSRB3 0x0000000B 0x00000000
R McASP0_DITCSRB4 0x0000000B 0x00000000
R McASP0_DITCSRB5 0x0000000B 0x00000000
R McASP0_DITUDRA0 0x0000000B 0x00000000
R McASP0_DITUDRA1 0x0000000B 0x00000000
R McASP0_DITUDRA2 0x0000000B 0x00000000
R McASP0_DITUDRA3 0x0000000B 0x00000000
R McASP0_DITUDRA4 0x0000000B 0x00000000
R McASP0_DITUDRA5 0x0000000B 0x00000000
R McASP0_DITUDRB0 0x0000000B 0x00000000
R McASP0_DITUDRB1 0x0000000B 0x00000000
R McASP0_DITUDRB2 0x0000000B 0x00000000
R McASP0_DITUDRB3 0x0000000B 0x00000000
R McASP0_DITUDRB4 0x0000000B 0x00000000
R McASP0_DITUDRB5 0x0000000B 0x00000000
R McASP0_SRCTL0 0x0000000B 0x00000000
R McASP0_SRCTL1 0x0000000B 0x00000000
R McASP0_SRCTL2 0x0000000B 0x00000000
R McASP0_SRCTL3 0x0000000B 0x00000000
R McASP0_SRCTL4 0x0000000B 0x00000000
R McASP0_SRCTL5 0x0000000B 0x00000000
R McASP0_SRCTL6 0x0000000B 0x00000000
R McASP0_SRCTL7 0x0000000B 0x00000019
R McASP0_SRCTL8 0x0000000B 0x00000000
R McASP0_SRCTL9 0x0000000B 0x00000000
R McASP0_SRCTL10 0x0000000B 0x00000000
R McASP0_SRCTL11 0x0000000B 0x00000000
R McASP0_SRCTL12 0x0000000B 0x00000000
R McASP0_SRCTL13 0x0000000B 0x00000000
R McASP0_SRCTL14 0x0000000B 0x00000000
R McASP0_SRCTL15 0x0000000B 0x0000002A
R McASP0_XBUF0 0x0000000B 0x00000000
R McASP0_XBUF1 0x0000000B 0x00000000
R McASP0_XBUF2 0x0000000B 0x00000000
R McASP0_XBUF3 0x0000000B 0x00000000
R McASP0_XBUF4 0x0000000B 0x00000000
R McASP0_XBUF5 0x0000000B 0x00000000
R McASP0_XBUF6 0x0000000B 0x00000000
R McASP0_XBUF7 0x0000000B 0x0FFFFFFF
R McASP0_XBUF8 0x0000000B 0x00000000
R McASP0_XBUF9 0x0000000B 0x00000000
R McASP0_XBUF10 0x0000000B 0x00000000
R McASP0_XBUF11 0x0000000B 0x00000000
R McASP0_XBUF12 0x0000000B 0x00000000
R McASP0_XBUF13 0x0000000B 0x00000000
R McASP0_XBUF14 0x0000000B 0x00000000
R McASP0_XBUF15 0x0000000B 0xFFEED400
R McASP0_RBUF0 0x0000000B 0x00000000
R McASP0_RBUF1 0x0000000B 0x00000000
R McASP0_RBUF2 0x0000000B 0x00000000
R McASP0_RBUF3 0x0000000B 0x00000000
R McASP0_RBUF4 0x0000000B 0x00000000
R McASP0_RBUF5 0x0000000B 0x00000000
R McASP0_RBUF6 0x0000000B 0x00000000
R McASP0_RBUF7 0x0000000B 0x0FFFFFFF
R McASP0_RBUF8 0x0000000B 0x00000000
R McASP0_RBUF9 0x0000000B 0x00000000
R McASP0_RBUF10 0x0000000B 0x00000000
R McASP0_RBUF11 0x0000000B 0x00000000
R McASP0_RBUF12 0x0000000B 0x00000000
R McASP0_RBUF13 0x0000000B 0x00000000
R McASP0_RBUF14 0x0000000B 0x00000000
R McASP0_RBUF15 0x0000000B 0xFFEED400

0 Sivaraj Kuppuraj over 9 years ago in reply to Sherry Ismail

TI__Mastermind 35645 points

Hi,

Glad that it is working. thanks for your update.

Regards,
Sivaraj K

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McASP Transmitter AXR is dead