AM1808 USB 2.0 Bulk IN Transactions - Clearing TXPKTRDY bit

Moving this to the AM1X forum.

Hi g.f,

Actually, this bit, TXPKTRDY  will get set in order to send the data. If this bit is already set, it will not allow any further transmission of data until the current transmission is either complete / denied .

Thus, it says that, it should get cleared after receiving the ACK.

But it will also get cleared in two other circumstances. That is , 1.  when the error count limit reached after NAK received  and 2. stall received.

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Hi Shankari,

Thank you for the reply.

I'm using USB as peripheral mode : Bulk In Transactions.
But the flow chart which you attached looks like it is appropriate to the Host mode.

Is this attached flow chart also same in Peripheral Mode: Bulk In Transactions?

best regards,
g.f.

Hi g.f,

That flowchart is for Host mode.

If it is in peripheral mode, Bulk IN Transactions, we have to refer the following regarding "TXPKTRDY" bit.

To answer your below question, I may need some more time looking into any of the peripheral mode driver code to confirm.

The following is the extract from TRM.

When data is to be transferred over a Bulk IN pipe, a data packet needs to be loaded into the FIFO and
the PERI_TXCSR register written to set the TXPKTRDY bit (bit 0). When the packet has been sent, the
TXPKTRDY bit will be cleared by the USB controller and an interrupt generated so that the next packet
can be loaded into the FIFO. If double packet buffering is enabled, then after the first packet has been
loaded and the TXPKTRDY bit set, the TXPKTRDY bit will immediately be cleared by the USB controller
and an interrupt generated so that a second packet can be loaded into the FIFO. The software should
operate in the same way, loading a packet when it receives an interrupt, regardless of whether double
packet buffering is enabled or not.
In the general case, the packet size must not exceed the size specified by the lower 11 bits of the
TXMAXP register. This part of the register defines the payload (packet size) for transfers over the USB
and is required by the USB Specification to be either 8, 16, 32, 64 (Full-Speed or High-Speed) or
512 bytes (High-Speed only).

The host may determine that all the data for a transfer has been sent by knowing the total amount of data
that is expected. Alternatively it may infer that all the data has been sent when it receives a packet which
is smaller than the stated payload (TXMAXP[10-0]). In the latter case, if the total size of the data block is a
multiple of this payload, it will be necessary for the function to send a null packet after all the data has
been sent. This is done by setting TXPKTRDY when the next interrupt is received, without loading any
data into the FIFO.
If large blocks of data are being transferred

--------------------------------------

Hi

<Edited >

As per my understanding, the TXPKTRDY bit of PERI_TXCSR is cleared once the packet has been sent irrespective of the ACK from the Host.


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Hi Shankari,

Thank you for the reply.

But my question is when TXPKTRDY will be "cleared".
>Q:
>After sending the packet, does USB controller clear TXPKTRDY bit
>after receiving ACK from the Host?
>Or does USB Controller clear TXPKTRDY bit as soon as PACKET is sent
>regardless of ACK from a host?

In AM1808 TRM(spruh82a) page.1582 "34.2.7.1.1.5 Endpoint 0 Service Routine",
it said as follow:
******************************************************************************
The controller clears the TXPKTRDY bit of PERI_CSR0 (bit 1) after the packet of data
in the FIFO has been successfully transmitted to the host.
******************************************************************************
How does USB controller will recognize that the packet of data
has been transmitted to the host successfully and clear the TXPKTRDY bit?
Isn't it ACK from the host?

best regards,
g.f.

Hi g.f.,

I have corrected / edited my previous post. I mistyped it as set instead of cleared. Request you to read again.

Hi Shankari,

Thank you for the screenshot.
I understood that TXPKTRDY bit of PERI_TXCSR get set and cleared.

I don't have USB logical analyser too.
I need to answer my customer as soon as possible and they want to know the specification of AM1808 USB Controller.
So, can I answer to my customer that TXPKTRDY bit of PERI_TXCSR will be cleared
once the packet has been sent irrespective of the ACK from the Host and this is a spec of AM1808 USB Controller?

best regards,
g.f.

Hi g.f.,

Yes Please. You can go-ahead and answer like that.


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Hi Shankari,

Thank you so much.
I will answer to my customer.

best regards,
g.f.