When comparing the steps for programming the C6748 PLL from power down as outlined in the System Reference Guide and the C6748 gel file provided with the C6748 EVM tools we have noticed a few differences.
Can some clarify which procedure is prefered?
SPRUGJ7D – TMS320C6748 DSP System Reference Guide
<<C6748.gel>
1. The C6748 gel file switches steps 1 & 2, for it switches the PLL to bypass mode before setting the CLKMODE bit.
Question: Does TI recommend that I follow the System Reference Guide (set CLKMODE bit then switch PLL to bypass mode) or follow the gel file example (switch PLL to bypass mode then set CLKMODE bit) that appears for the most part to work on the C6748 EVM?
2. The C6748 gel file code example disables the PLL output prior to powering up the PLL (step 4), after which it then enables the PLL output. There doesn’t appear to be any mention of disabling the PLL prior to step 4 or enabling the PLL after step 4 in the System Reference Guide. From one perspective, the PLL is in bypass mode at this time in the setup sequence so it doesn’t seem necessary to disable and then enable the PLL output around step 4. On the other hand, there could be an undocumented issue I cannot find in the System Reference Guide yet that these extra steps address. Additionally, the register bit in question is actually identified as a reserved bit in the System Reference Guide.
Question: Does TI recommend that I follow the System Reference Guide (ignore disabling and enabling around step 4) or follow the C6748 gel file example code (enable and disable PLL output around step 4)?
3. The C6748 gel file example code also includes a PLL stabilization wait time and a PLL reset wait time. Again I do not find mention of this in the System Reference Guide.
Question: Does TI recommend that I ignore these two wait loops as per the gel file code comments?
