• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 384 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3703 Drive Strength Registers

Mark Ackerson
Genius 10190 points
Other Parts Discussed in Thread: AM3703

Customer is investigating changing the drive strength of AM3703 SDRAM to reduce EMI.  They've tried a couple of methods of setting drive strength registers to configure drive strength  to 1/8, 1/2, and full.  However, they have yet to see any change to slew rate with these changes.  With the latest attempt they set both of the sdrc_emr2_0 and sdrc_emr2_1 registers to 0xE0 on one unit and  0x00 on another unit to set the drive strength to 1/8th and full.  When testing these units there was no change to the slew rate.  Would you be able to help us figure out how to set the registers to change the drive strength of our units to full, half , 1/4th, and 1/8th?  Current register values are the following.

prog_io0                     - 0x0
prog_io1                     - 0x100001
prog_io2                     - 0x2220080
prog_io_wkup1           - 0x0
sdrc_emr2_0              - 0x20
sdrc_emr2_1              - 0x20
sdrc_Syscfg               - 0x10


Thanks,

Mark

  • 0
    TI__Guru*** 125430 points
    Mark,

    I provided some of the details in this post:

    e2e.ti.com/.../1623882

    Specifically: The AM37xx SDRC drive strength is controlled by the CONTROL_PROG_IO0 register. The LPDDR drive strength is controlled by the SDRC_EMR2 register (DS bits).

    So right now, looking at bits 7:5 of emr2 it looks like you have 1/2 strength configured. For full strength you would use emsr2=0. For 3/4 strength you would use emr2=0x80.

    Note that quarter and eighth strength are OPTIONAL so you must verify that the specific LPDDR chosen by your customer supports those fields. Also, you should double check that the memory vendor is using these same definitions in the EMR2 register, i.e. the EMR2 register in the LPDDR data manual should match up bit for bit with the AM37xx register. I've seen a couple odd-ball cases where the DS bits were defined slightly different than ours. Note the definitions in the AM37xx TRM come from the JEDEC LPDDR standard.