DM365 Audio clarification

Hi,

Please refer to the document SPRS457C page 60. The McBSP module clock is driven by the SYSCLK4 (Peripheral System Clock Bus). If the SYSCLK4 can be divisible by the 48Khz (frame) and 3.072Mhz (serial clock) then these frequencies can be generated in the clock generation circuitry. Otherwise an external clock should be used for this audio type application to source the CLKX or CLKR.

Thanks.

Thanks Tai. What is the clock ratio between the clock coming into the McBSP and the bit clock of the audio data.

Yes. You are correct. You need a clock equals to multiple of that clock frequency since the Sample Rate Generator has no multiplier but just a divider.

Thanks.

You can find the info in the Data Sheet (SPRS475C) on page 83. It has input clock operating recommended specs for crystals and oscillator. For the PLL multiplier, please refer to the SPRUFG5.

Thanks.

These choices do not allow me to create at 12.288 MHz clock output for my audio  device.  If I know the allowable range for the clock input and PLL output, I can determine if there is a combination that will allow me to create this clock.

Hi Michael,

It is more than that. The clock generated by the PLL (SYSCLK4) is used by other peripherals too. Even if you can find one that works with the audio device, it might not work for other peripherals.

I suggest to use an external 12.288Mhz (or a multiple of that) clock as a source for the McBSP CLKX or CLKR to generate just for the McBSP clock and frame to handle the audio data.

Thanks. 

I understand the significance of changes here.  All I am asking is for the the specifications for the PLL.  Are they available?

Hi Michael,

The PLL spec is included in the ARM Subsystem document (SPRUFG5A). It is discussed in section 6, page 35.

Hope this helps.

Thanks.

Hi Tai,

Michael and I have not been able to find the PLL specifications. What Mike is looking for are the input clock rate and the minimum and maximum output frequencies for the PLL - can you point Mike to where we can find this?

They are trying to figure out if the issues they are seeing are due to PLL limitations on our part.

Hi ghunathanrini,

You should be able to obtain all the info needed from the data sheet (SPRS457C), section 3.3, Table 6-3 and Table 6-4. From these tables, you can pick the input clock frequency depend on oscillator vs. crystal type and the crystal ESR if the crystal is picked. The output PLL frequency will be 2XPLLM but this frequency cannot exceed the maximum operating frequency of the device i.e. -300, -270, -216.

Hope this helps.

Thanks,

Tai

These are only the standard frequencies and they don't consider the DM368.

I guess it is not possible to just get the information I am asking for.

Michael,

For DM368, specifically, you should be looking at the DM368 Datasheet, SPRS668A, located here:  http://www.ti.com/lit/gpn/tms320dm368

Michael,

Some additional information on the input frequency that the internall oscillators can take is described in the Datasheet mentioned by Jeff above in section 6.6.2 min 19.2mhz to max 36mhz.  Any frequency in between that range and not listed in the examples in 3.3.6 can impact the clks for other peripherals that are frequency sensitive(such as the ones listed in Table 3-5 in the datasheet). This applies to dm365 or dm368 whichever device you are planning to use in your system. 

The output PLL frequencies (as shown in chapter 3.3.6) are:

PLLOUT for dm365<600Mhz

PLLOUT for dm368<680Mhz

So as long is the input clock  is within the specification listed above, I can use any input divider settings?  I can put a 19.2 MHz input clock and divide is as by as much as 32 (maximum setting in PREDIV register).  So the input to the PLL can tolerate an input frequency of as low as 600 KHz if I understand these specifications correctly.

Also, is there a minimum PLL frequency?