Hi Biser,
We are using multiple GPMC CS for different interface for external memory access.
GPMC CS0 - NAND flash
GPMC CS1 - Audio codec(AC49008)
GPMC CS2 - DSP(TMS320V5502)
While I was going through AM3352 data sheet , I am having a query about below statement,
"NAND (8-bit and 16-bit) memory devices using a standard NAND asynchronous address/data-multiplexing
scheme can be supported on any chip-select with the appropriate asynchronous configuration settings
As for any other type of memory compatible with the GPMC interface, accesses to a chip-select allocated
to a NAND device can be interleaved with accesses to chip-selects allocated to other external devices.
This interleaved capability limits the system to chip enable don't care NAND devices, because the chip-
select allocated to the NAND device must be de-asserted if accesses to other chip-selects are requested.
"
This statement means -> When system accessing NAND flash with CS0 at that time if anyother CS request (CS1 and CS2) occurs at that time system will deassert first CS0 and then it will run the other request.
OR:
First system will complete the CS0 access for the system and then it will server for CS1 or CS2.
Regards,
Santosh Rai.
