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AM3352 DDR3 DQS Skew

PSB
Prodigy 220 points
Other Parts Discussed in Thread: AM3352

I’m looking at the Sitara (AM3352) routing rules for DDR3 (AM3352 datasheet para 7.7.2.3.3).  Table 7-67 shows skew for the DQS group to be 25mils.  I have two questions:

 

1)    Is this a +/- skew (i.e. total skew within the group therefore is 50 mils).  Or is the total skew within the group 25 mils? 

2)    Are via lengths counted in the skew?  I noticed that the BBB design has several DDR signals with no vias, although most have two vias.  The inclusion of via lengths would increase the length by 62mils for each via.  Therefore the trace length would have to be reduced to take via length into account.

Can someone clarify?

Thanks,

PSB