C6678 TSIP clock frequency

Aleksandr Lisovich

Hi All,

I am considering the possibility to use the TSIP interface to acquire data from multiple ADCs and have the first likely naive question to start:

The clock frequency is external for TSIP, i.e. one might think it can be arbitrary. However the TSIP docs clearly state the frequency should be of fixed values (8.192 MHz, 16.384 etc). So, is it possible to use arbitrary clock frequency or the internal circuitry (like time delays etc.) really expects exact frequency values? Also, if this is the case, what are the tolerances for exact external frequencies (like 8.192 MHz +- )?

Best Regards,

Alex

over 10 years ago

0 Senthilkumar Srinivasan over 10 years ago

TI__Mastermind 43660 points

Alex,

Please refer Table 7-75 and 7-76 in the device data manual for TSIP clock timing requirements. Are you expecting frequency stability in ppm for TSIP clock ?

Regards,
Senthil

0 Aleksandr Lisovich over 10 years ago in reply to Senthilkumar Srinivasan

Intellectual 325 points

Hi Senthil,

Thank you very much for your response!

I took a look at the tables and not sure how they address my questions.

1. For example, in table 7.75, line 1, t(CLK) has MIN value of 61ns (corresponds to 16.384 MHz), but no MAX value. Does it mean it can be of any value greater than 61ns or it should be exactly 61ns?

2. The tolerances for frequencies in case only fixed values for frequencies are allowed, i.e. 8.192 MHz, 16.384 MHz etc .
What I mean talking about tolerances is : can this frequency be 8.185 MHz instead of 8.192 MHz for example? Or another words, every oscillator has deviation from ideal frequency, what is the maximum allowable deviation?

Best Regards,

Alex

0 Senthilkumar Srinivasan over 10 years ago in reply to Aleksandr Lisovich

TI__Mastermind 43660 points

Alex,

1. I will check on the Max value and update you.

2. The deviation in frequency is denoted by the term frequency stability in ppm. This is not specifically mentioned for TSIP clock. However the input clocks have +/- 100 ppm, so this should be applicable for TSIP clock as well. The +/- 100 ppm is equivalent to +/- 0.01%.

Regards,
Senthil

0 Aleksandr Lisovich over 10 years ago in reply to Senthilkumar Srinivasan

Intellectual 325 points

Thank you, Senthil!

Waiting for an update.

Best Regards,

Alex

0 Aleksandr Lisovich over 10 years ago in reply to Aleksandr Lisovich

Intellectual 325 points

Hi Senthil,

Do you have any updates on the Max value?

Regards,
Alex

0 Senthilkumar Srinivasan over 10 years ago in reply to Aleksandr Lisovich

TI__Mastermind 43660 points

Alex,

I am waiting for the inputs from the internal team. I will update you once i get a response.

Regards,
Senthil

0 Senthilkumar Srinivasan over 9 years ago in reply to Aleksandr Lisovich

TI__Mastermind 43660 points

Alex,

Here is the response from internal team.

Even though TSIP can be run at higher speeds, it was only ever characterized and validated at the serial data rates of 8.192Mbps, 16.384Mbps and 32.768Mbps. Therefore, the maximum clock rate in 1X mode is 32.768MHz or 65.536MHz in 2X mode.

Regards,
Senthil

0 Aleksandr Lisovich over 9 years ago in reply to Senthilkumar Srinivasan

Intellectual 325 points

Senthil,

Thank you very much for your response.

However my question was a little bit different. It was about maximum PERIOD, not maximum frequency. The question was: "in table 7.75, line 1, t(CLK) has MIN value of 61ns (corresponds to 16.384 MHz), but no MAX value. Does it mean it can be of any value greater than 61ns or it should be exactly 61ns?".

Greater period corresponds to the LOWER frequency. So my question was: can TSIP be operated at the lower frequencies, for example, 5MHz instead of 8.192MHz etc.

Could you verify this for me? You help is greatly appreciated as usual.

Best Regards,

Alex

0 Tom Johnson 16214 over 9 years ago in reply to Aleksandr Lisovich

TI__Mastermind 46460 points

Alex,

The TSIP interface is targeted for telephony applications that use the standard rates listed. Therefore, the qualification is only targeted toward that application. However, TSIP is a fully synchronous interface that is not bound to any clock rate. It is characterized for operation up to 32.768MHz in 1x clock mode and 65.536MHz in 2x clock mode.

Tom

0 Aleksandr Lisovich over 9 years ago in reply to Tom Johnson 16214

Intellectual 325 points

Thank you, Tom!

This perfectly answers my question.

Best Regards,

Alex

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C6678 TSIP clock frequency