I am using C6748 for I2S in/out. For streaming data out, I am using following code,
else if ((mcaspRegs->XSTAT & 0x00000020)) //XBUF ready
{
if ((mcaspRegs->XSTAT & 0x00000040))
{
mcaspRegs->XBUF7 = sample_left;//0x55555555
mcaspRegs->XSTAT = 0x00000040;
}
else
{
mcaspRegs->XBUF7 = sample_right;//0x7FFFFFFF
mcaspRegs->XSTAT = 0x00000010;
}
mcaspRegs->XSTAT = 0x00000020;
}
But on oscilloscope, I see that the start of frame sync ( which is one word long in my case) has sample_right transmitted and last slot has sample_left. Why are the outputs interchanged? Is the delay to move data from XBUFn to XSRn one sample long? Does the 'current time slot' mean the slot clocking out or the slot getting ready?
