GPMC Synchronous 16 bit address/data multiplexed memory init

Hi,

TI cannot say what timings you will need to connect to an FPGA. You will need to determine the timings according to your FPGA configuration/requirements. Note that the GPMC clock cannot be used for FPGA system clock. GPMC clock is not a continuous clock source, it's present on the AM437X pin only during GPMC accesses. To understand how timings are calculated please refer to section 5.12.8.1 from the AM437X Datasheet Rev. B and section 9.1 from the AM437X TRM Rev. D.

Hi Biser,

" Note that the GPMC clock cannot be used for FPGA system clock"
in AM4379, GPMC clock frequency is derived from L3 clock right ?In section, "9.1.3.3.1 GPMC Clock Configuration ",it is given that maximum prcm_gpmc_clk is 100Mhz.To generate 50Mhz external clock to synchronize external memory devices,we have to use GPMCFCLKDIVIDER as 1.

We checked the section "9.1.5.1.3 GPMC Configuration for Synchronous Burst Read Access " to configure the timing details.
But there it is given that " The clock runs at 104 MHz ( f = 104 MHz; T = 9, 615 ns) "

what is this 104 Mhz? maximum is 100 Mhz right?

The max. GPMC clock frequency is 100MHz. See section 9.1.2.2 of the TRM and Table 5-40 on page 150 of the Datasheet. 104MHz is a typo.

Hi Biser,
To set the timing parameter for GPMC access, we checked the following section.
9.1.5.1 How to Set GPMC Timing Parameters for Typical Accesses.

in the above section, it is given that
The example is based on a 512-Mb multiplexed NOR flash memory with the following characteristics:
• Type: NOR flash (address/data-multiplexed mode)
• Size: 512M bits
• Data Bus: 16 bits wide
• Speed: 104 MHz clock frequency
• Read access time: 80 ns

The above mentioned speed(104 Mhz) is a typo error?

Regards,
Jinu

Yes, it should be 100MHz.

Hi Biser,

Thanks for the reply. One more clarity required
We are referring to two clocks.
1)GPMC_FCLK-Internal Functional and interface clock. Acts as the time reference.
2)GPMC_CLK - External clock provided to the external device for synchronous operations
Here GPMC_CLK is derived from GPMC_FCLK.

Speed: 104 MHz (100Mhz)clock frequency refers to GPMC FCLK right?

You can see section 5.2.6.3.1.1 from the TRM too, it will probably help (GPMC initialization for NOR boot, timings are given in the table).