mcbsp dm814x ..initialization process

Muhammad Tariq

Other Parts Discussed in Thread: SYSCONFIG

hi everyone

i am trying to implement a simple loopback test for mcbsp module of dm814x using code composer studio.I have gone through previous posts regarding bug of base address of mcbsp module which in trm nd datasheet is 4700_0000 but according to a few persons at e2e its 47000100 though i have tried to initialized mcbsp module with both addresses still its not working.My main problem is that if i am setting a specific register by writing some values ,it is not writing there but writing somewhere else and in few registers which are completely writeable but i am not able to write them.Attaching my code as well .kindly respond with appropriate answers.

regards.

//header file // declarations//mcbcp.h

/*
* mcbsp.h
*
* Created on: 02.11.2015
* Author: x0233221
*/

#ifndef MCBSP_H_
#define MCBSP_H_

#ifdef __cplusplus
extern "C" {
#endif

#include "DM814x_SoC.h"
#include "DM814x_types.h"

#define MCBSP_BASE_ADDRESS 0x47000100
#define MCBSP_END_ADDRESS 0x473FFFFF //4MB

//#define MCBSP_REVNB_OFFSET 0x47000000
//#define MCBSP_SYSCONFIG_REG_OFFSET 0x47000010
//#define MCBSP_EOI_OFFSET 0x47000020
//#define MCBSP_IRQSTATUS_RAW_OFFSET 0x47000024
//#define MCBSP_IRQSTATUS_OFFSET 0x47000028
//#define MCBSP_IRQENABLE_SET_OFFSET 0x4700002C
//#define MCBSP_IRQENABLE_CLR_OFFSET 0x47000030
//#define MCBSP_DMARXENABLE_SET_OFFSET 0x47000034
//#define MCBSP_DMATXENABLE_SET_OFFSET 0x47000038
//#define MCBSP_DMARXENABLE_CLR_OFFSET 0x4700003C
//#define MCBSP_DMATXENABLE_CLR_OFFSET 0x47000040
//#define MCBSP_DMARXWAKE_EN_OFFSET 0x47000048
//#define MCBSP_DMATXWAKE_EN_OFFSET 0x4700004C

#define MCBSP_DRR_REG_OFFSET 0x47000100
#define MCBSP_DXR_REG_OFFSET 0x47000108
#define MCBSP_SPCR2_REG_OFFSET 0x47000110
#define MCBSP_SPCR1_REG_OFFSET 0x47000114
#define MCBSP_RCR2_REG_OFFSET 0x47000118
#define MCBSP_RCR1_REG_OFFSET 0x4700011C
#define MCBSP_XCR2_REG_OFFSET 0x47000120
#define MCBSP_XCR1_REG_OFFSET 0x47000124
#define MCBSP_SRGR2_REG_OFFSET 0x47000128
#define MCBSP_SRGR1_REG_OFFSET 0x4700012C
#define MCBSP_MCR2_REG_OFFSET 0x47000130
#define MCBSP_MCR1_REG_OFFSET 0x47000134
#define MCBSP_RCERA_REG_OFFSET 0x47000138
#define MCBSP_RCERB_REG_OFFSET 0x4700013C
#define MCBSP_XCERA_REG_OFFSET 0x47000140
#define MCBSP_XCERB_REG_OFFSET 0x47000144
#define MCBSP_PCR_REG_OFFSET 0x47000148
#define MCBSP_RCERC_REG_OFFSET 0x4700014C
#define MCBSP_RCERD_REG_OFFSET 0x47000150
#define MCBSP_XCERC_REG_OFFSET 0x47000154
#define MCBSP_XCERD_REG_OFFSET 0x47000158
#define MCBSP_RCERE_REG_OFFSET 0x4700015C
#define MCBSP_RCERF_REG_OFFSET 0x47000160
#define MCBSP_XCERE_REG_OFFSET 0x47000164
#define MCBSP_XCERF_REG_OFFSET 0x47000168
#define MCBSP_RCERG_REG_OFFSET 0x4700016C
#define MCBSP_RCERH_REG_OFFSET 0x47000170
#define MCBSP_XCERG_REG_OFFSET 0x47000174
#define MCBSP_XCERH_REG_OFFSET 0x47000178
#define MCBSP_REV_REG_OFFSET 0x4700017C
#define MCBSP_RINTCLR_REG_OFFSET 0x47000180
#define MCBSP_XINTCLR_REG_OFFSET 0x47000184
#define MCBSP_ROVFLCLR_REG_OFFSET 0x47000188
#define MCBSP_SYSCONFIG_REG_OFFSET 0x4700018C
#define MCBSP_THRSH2_REG_OFFSET 0x47000190
#define MCBSP_THRSH1_REG_OFFSET 0x47000194
#define MCBSP_IRQSTATUS_OFFSET 0x470001A0
#define MCBSP_IRQENABLE_OFFSET 0x470001A4
#define MCBSP_WAKEUP_EN_OFFSET 0x470001A8
#define MCBSP_XCCR_REG_OFFSET 0x470001AC
#define MCBSP_RCCR_REG_OFFSET 0x470001B0
#define MCBSP_XBUFFSTAT_REG_OFFSET 0x470001B4
#define MCBSP_RBUFFSTAT_REG_OFFSET 0x470001B8
#define MCBSP_STATUS_REG_OFFSET 0x470001C0

// MCBSPLP_SPCR2_REG
#define SPCR2_FREE (0x0200)
#define SPCR2_SOFT (0x0100)
#define SPCR2_FRST (0x0080)
#define SPCR2_GRST (0x0040)
#define SPCR2_XINTM_1 (0x0020)
#define SPCR2_XINTM_0 (0x0010)
#define SPCR2_XSYNCERR (0x0008)
#define SPCR2_XEMPTY (0x0004)
#define SPCR2_XRDY (0x0002)
#define SPCR2_XRST (0x0001)

// MCBSPLP_SPCR1_REG
#define SPCR1_ALB (0x8000)
#define SPCR1_RJUST_1 (0x4000)
#define SPCR1_RJUST_0 (0x2000)
#define SPCR1_DXENA (0x0080)
#define SPCR1_RINTM_1 (0x0020)
#define SPCR1_RINTM_0 (0x0010)
#define SPCR1_RSYNCERR (0x0008)
#define SPCR1_RFULL (0x0004)
#define SPCR1_RRDY (0x0002)
#define SPCR1_RRST (0x0001)

// MCBSPLP_RCR2_REG
#define RCR2_RPHASE (0x8000)
#define RCR2_RFRLEN2_6 (0x4000)
#define RCR2_RFRLEN2_5 (0x2000)
#define RCR2_RFRLEN2_4 (0x1000)
#define RCR2_RFRLEN2_3 (0x0800)
#define RCR2_RFRLEN2_2 (0x0400)
#define RCR2_RFRLEN2_1 (0x0200)
#define RCR2_RFRLEN2_0 (0x0100)
#define RCR2_RWDLEN2_2 (0x0080)
#define RCR2_RWDLEN2_1 (0x0040)
#define RCR2_RWDLEN2_0 (0x0020)
#define RCR2_RREVERSE_1 (0x0010)
#define RCR2_RREVERSE_0 (0x0008)
#define RCR2_RDATDLY_1 (0x0002)
#define RCR2_RDATDLY_0 (0x0001)

// MCBSPLP_RCR1_REG
#define RCR1_RFRLEN1_6 (0x4000)
#define RCR1_RFRLEN1_5 (0x2000)
#define RCR1_RFRLEN1_4 (0x1000)
#define RCR1_RFRLEN1_3 (0x0800)
#define RCR1_RFRLEN1_2 (0x0400)
#define RCR1_RFRLEN1_1 (0x0200)
#define RCR1_RFRLEN1_0 (0x0100)
#define RCR1_RWDLEN1_2 (0x0080)
#define RCR1_RWDLEN1_1 (0x0040)
#define RCR1_RWDLEN1_0 (0x0020)

// MCBSPLP_XCR2_REG
#define XCR2_XPHASE (0x8000)
#define XCR2_XFRLEN2_6 (0x4000)
#define XCR2_XFRLEN2_5 (0x2000)
#define XCR2_XFRLEN2_4 (0x1000)
#define XCR2_XFRLEN2_3 (0x0800)
#define XCR2_XFRLEN2_2 (0x0400)
#define XCR2_XFRLEN2_1 (0x0200)
#define XCR2_XFRLEN2_0 (0x0100)
#define XCR2_XWDLEN2_2 (0x0080)
#define XCR2_XWDLEN2_1 (0x0040)
#define XCR2_XWDLEN2_0 (0x0020)
#define XCR2_XREVERSE_1 (0x0010)
#define XCR2_XREVERSE_0 (0x0008)
#define XCR2_XDATDLY_1 (0x0002)
#define XCR2_XDATDLY_0 (0x0001)

// MCBSPLP_XCR1_REG
#define XCR1_XFRLEN1_6 (0x4000)
#define XCR1_XFRLEN1_5 (0x2000)
#define XCR1_XFRLEN1_4 (0x1000)
#define XCR1_XFRLEN1_3 (0x0800)
#define XCR1_XFRLEN1_2 (0x0400)
#define XCR1_XFRLEN1_1 (0x0200)
#define XCR1_XFRLEN1_0 (0x0100)
#define XCR1_XWDLEN1_2 (0x0080)
#define XCR1_XWDLEN1_1 (0x0040)
#define XCR1_XWDLEN1_0 (0x0020)

// MCBSPLP_SRGR2_REG
#define SRGR2_GSYNC (0x8000)
#define SRGR2_CLKSP (0x4000)
#define SRGR2_CLKSM (0x2000)
#define SRGR2_FSGM (0x1000)
#define SRGR2_FPER_b (0x0800)
#define SRGR2_FPER_a (0x0400)
#define SRGR2_FPER_9 (0x0200)
#define SRGR2_FPER_8 (0x0100)
#define SRGR2_FPER_7 (0x0080)
#define SRGR2_FPER_6 (0x0040)
#define SRGR2_FPER_5 (0x0020)
#define SRGR2_FPER_4 (0x0010)
#define SRGR2_FPER_3 (0x0008)
#define SRGR2_FPER_2 (0x0004)
#define SRGR2_FPER_1 (0x0002)
#define SRGR2_FPER_0 (0x0001)
#define SRGR2_FPER_MASK (0xFFF)
#define SRGR2_FPER_BIT (0)

// MCBSPLP_SRGR1_REG
#define SRGR1_FWID_7 (0x8000)
#define SRGR1_FWID_6 (0x4000)
#define SRGR1_FWID_5 (0x2000)
#define SRGR1_FWID_4 (0x1000)
#define SRGR1_FWID_3 (0x0800)
#define SRGR1_FWID_2 (0x0400)
#define SRGR1_FWID_1 (0x0200)
#define SRGR1_FWID_0 (0x0100)
#define SRGR1_CLKGDV_7 (0x0080)
#define SRGR1_CLKGDV_6 (0x0040)
#define SRGR1_CLKGDV_5 (0x0020)
#define SRGR1_CLKGDV_4 (0x0010)
#define SRGR1_CLKGDV_3 (0x0008)
#define SRGR1_CLKGDV_2 (0x0004)
#define SRGR1_CLKGDV_1 (0x0002)
#define SRGR1_CLKGDV_0 (0x0001)
#define SRGR1_FWID_MASK (0xFF00)
#define SRGR1_CLKGDV_MASK (0x00FF)
#define SRGR1_FWID_BIT (8)
#define SRGR1_CLKGDV_BIT (0)

// MCBSPLP_MCR2_REG
#define MCR2_XMCME (0x0200)
#define MCR2_XPBBLK_1 (0x0100)
#define MCR2_XPBBLK_0 (0x0080)
#define MCR2_XPABLK_1 (0x0040)
#define MCR2_XPABLK_0 (0x0020)
#define MCR2_XMCM_1 (0x0002)
#define MCR2_XMCM_0 (0x0001)

// MCBSPLP_MCR1_REG
#define MCR1_RMCME (0x0200)
#define MCR1_RPBBLK_1 (0x0100)
#define MCR1_RPBBLK_0 (0x0080)
#define MCR1_RPABLK_1 (0x0040)
#define MCR1_RPABLK_0 (0x0020)
#define MCR1_RMCM (0x0001)

// MCBSPLP_RCERA_REG
#define RCERA_F (0x8000)
#define RCERA_E (0x4000)
#define RCERA_D (0x2000)
#define RCERA_C (0x1000)
#define RCERA_B (0x0800)
#define RCERA_A (0x0400)
#define RCERA_9 (0x0200)
#define RCERA_8 (0x0100)
#define RCERA_7 (0x0080)
#define RCERA_6 (0x0040)
#define RCERA_5 (0x0020)
#define RCERA_4 (0x0010)
#define RCERA_3 (0x0008)
#define RCERA_2 (0x0004)
#define RCERA_1 (0x0002)
#define RCERA_0 (0x0001)

// MCBSPLP_RCERB_REG
#define RCERB_F (0x8000)
#define RCERB_E (0x4000)
#define RCERB_D (0x2000)
#define RCERB_C (0x1000)
#define RCERB_B (0x0800)
#define RCERB_A (0x0400)
#define RCERB_9 (0x0200)
#define RCERB_8 (0x0100)
#define RCERB_7 (0x0080)
#define RCERB_6 (0x0040)
#define RCERB_5 (0x0020)
#define RCERB_4 (0x0010)
#define RCERB_3 (0x0008)
#define RCERB_2 (0x0004)
#define RCERB_1 (0x0002)
#define RCERB_0 (0x0001)

// MCBSPLP_XCERA_REG
#define XCERA_F (0x8000)
#define XCERA_E (0x4000)
#define XCERA_D (0x2000)
#define XCERA_C (0x1000)
#define XCERA_B (0x0800)
#define XCERA_A (0x0400)
#define XCERA_9 (0x0200)
#define XCERA_8 (0x0100)
#define XCERA_7 (0x0080)
#define XCERA_6 (0x0040)
#define XCERA_5 (0x0020)
#define XCERA_4 (0x0010)
#define XCERA_3 (0x0008)
#define XCERA_2 (0x0004)
#define XCERA_1 (0x0002)
#define XCERA_0 (0x0001)

// MCBSPLP_XCERB_REG
#define XCERB_F (0x8000)
#define XCERB_E (0x4000)
#define XCERB_D (0x2000)
#define XCERB_C (0x1000)
#define XCERB_B (0x0800)
#define XCERB_A (0x0400)
#define XCERB_9 (0x0200)
#define XCERB_8 (0x0100)
#define XCERB_7 (0x0080)
#define XCERB_6 (0x0040)
#define XCERB_5 (0x0020)
#define XCERB_4 (0x0010)
#define XCERB_3 (0x0008)
#define XCERB_2 (0x0004)
#define XCERB_1 (0x0002)
#define XCERB_0 (0x0001)

// MCBSPLP_PCR_REG
#define PCR_IDLE_EN (0x4000)
#define PCR_XIOEN (0x2000)
#define PCR_RIOEN (0x1000)
#define PCR_FSXM (0x0800)
#define PCR_FSRM (0x0400)
#define PCR_CLKXM (0x0200)
#define PCR_CLKRM (0x0100)
#define PCR_SCLKME (0x0080)
#define PCR_CLKS_STAT (0x0040)
#define PCR_DX_STAT (0x0020)
#define PCR_DR_STAT (0x0010)
#define PCR_FSXP (0x0008)
#define PCR_FSRP (0x0004)
#define PCR_CLKXP (0x0002)
#define PCR_CLKRP (0x0001)

// MCBSPLP_RCERC_REG
#define RCERC_F (0x8000)
#define RCERC_E (0x4000)
#define RCERC_D (0x2000)
#define RCERC_C (0x1000)
#define RCERC_B (0x0800)
#define RCERC_A (0x0400)
#define RCERC_9 (0x0200)
#define RCERC_8 (0x0100)
#define RCERC_7 (0x0080)
#define RCERC_6 (0x0040)
#define RCERC_5 (0x0020)
#define RCERC_4 (0x0010)
#define RCERC_3 (0x0008)
#define RCERC_2 (0x0004)
#define RCERC_1 (0x0002)
#define RCERC_0 (0x0001)

// MCBSPLP_RCERD_REG
#define RCERD_F (0x8000)
#define RCERD_E (0x4000)
#define RCERD_D (0x2000)
#define RCERD_C (0x1000)
#define RCERD_B (0x0800)
#define RCERD_A (0x0400)
#define RCERD_9 (0x0200)
#define RCERD_8 (0x0100)
#define RCERD_7 (0x0080)
#define RCERD_6 (0x0040)
#define RCERD_5 (0x0020)
#define RCERD_4 (0x0010)
#define RCERD_3 (0x0008)
#define RCERD_2 (0x0004)
#define RCERD_1 (0x0002)
#define RCERD_0 (0x0001)

// MCBSPLP_XCERC_REG
#define XCERC_F (0x8000)
#define XCERC_E (0x4000)
#define XCERC_D (0x2000)
#define XCERC_C (0x1000)
#define XCERC_B (0x0800)
#define XCERC_A (0x0400)
#define XCERC_9 (0x0200)
#define XCERC_8 (0x0100)
#define XCERC_7 (0x0080)
#define XCERC_6 (0x0040)
#define XCERC_5 (0x0020)
#define XCERC_4 (0x0010)
#define XCERC_3 (0x0008)
#define XCERC_2 (0x0004)
#define XCERC_1 (0x0002)
#define XCERC_0 (0x0001)

// MCBSPLP_XCERD_REG
#define XCERD_F (0x8000)
#define XCERD_E (0x4000)
#define XCERD_D (0x2000)
#define XCERD_C (0x1000)
#define XCERD_B (0x0800)
#define XCERD_A (0x0400)
#define XCERD_9 (0x0200)
#define XCERD_8 (0x0100)
#define XCERD_7 (0x0080)
#define XCERD_6 (0x0040)
#define XCERD_5 (0x0020)
#define XCERD_4 (0x0010)
#define XCERD_3 (0x0008)
#define XCERD_2 (0x0004)
#define XCERD_1 (0x0002)
#define XCERD_0 (0x0001)

// MCBSPLP_RCERE_REG
#define RCERE_F (0x8000)
#define RCERE_E (0x4000)
#define RCERE_D (0x2000)
#define RCERE_C (0x1000)
#define RCERE_B (0x0800)
#define RCERE_A (0x0400)
#define RCERE_9 (0x0200)
#define RCERE_8 (0x0100)
#define RCERE_7 (0x0080)
#define RCERE_6 (0x0040)
#define RCERE_5 (0x0020)
#define RCERE_4 (0x0010)
#define RCERE_3 (0x0008)
#define RCERE_2 (0x0004)
#define RCERE_1 (0x0002)
#define RCERE_0 (0x0001)

// MCBSPLP_RCERF_REG
#define RCERF_F (0x8000)
#define RCERF_E (0x4000)
#define RCERF_D (0x2000)
#define RCERF_C (0x1000)
#define RCERF_B (0x0800)
#define RCERF_A (0x0400)
#define RCERF_9 (0x0200)
#define RCERF_8 (0x0100)
#define RCERF_7 (0x0080)
#define RCERF_6 (0x0040)
#define RCERF_5 (0x0020)
#define RCERF_4 (0x0010)
#define RCERF_3 (0x0008)
#define RCERF_2 (0x0004)
#define RCERF_1 (0x0002)
#define RCERF_0 (0x0001)

// MCBSPLP_XCERE_REG
#define XCERE_F (0x8000)
#define XCERE_E (0x4000)
#define XCERE_D (0x2000)
#define XCERE_C (0x1000)
#define XCERE_B (0x0800)
#define XCERE_A (0x0400)
#define XCERE_9 (0x0200)
#define XCERE_8 (0x0100)
#define XCERE_7 (0x0080)
#define XCERE_6 (0x0040)
#define XCERE_5 (0x0020)
#define XCERE_4 (0x0010)
#define XCERE_3 (0x0008)
#define XCERE_2 (0x0004)
#define XCERE_1 (0x0002)
#define XCERE_0 (0x0001)

// MCBSPLP_XCERF_REG
#define XCERF_F (0x8000)
#define XCERF_E (0x4000)
#define XCERF_D (0x2000)
#define XCERF_C (0x1000)
#define XCERF_B (0x0800)
#define XCERF_A (0x0400)
#define XCERF_9 (0x0200)
#define XCERF_8 (0x0100)
#define XCERF_7 (0x0080)
#define XCERF_6 (0x0040)
#define XCERF_5 (0x0020)
#define XCERF_4 (0x0010)
#define XCERF_3 (0x0008)
#define XCERF_2 (0x0004)
#define XCERF_1 (0x0002)
#define XCERF_0 (0x0001)

// MCBSPLP_RCERG_REG
#define RCERG_F (0x8000)
#define RCERG_E (0x4000)
#define RCERG_D (0x2000)
#define RCERG_C (0x1000)
#define RCERG_B (0x0800)
#define RCERG_A (0x0400)
#define RCERG_9 (0x0200)
#define RCERG_8 (0x0100)
#define RCERG_7 (0x0080)
#define RCERG_6 (0x0040)
#define RCERG_5 (0x0020)
#define RCERG_4 (0x0010)
#define RCERG_3 (0x0008)
#define RCERG_2 (0x0004)
#define RCERG_1 (0x0002)
#define RCERG_0 (0x0001)

// MCBSPLP_RCERH_REG
#define RCERH_F (0x8000)
#define RCERH_E (0x4000)
#define RCERH_D (0x2000)
#define RCERH_C (0x1000)
#define RCERH_B (0x0800)
#define RCERH_A (0x0400)
#define RCERH_9 (0x0200)
#define RCERH_8 (0x0100)
#define RCERH_7 (0x0080)
#define RCERH_6 (0x0040)
#define RCERH_5 (0x0020)
#define RCERH_4 (0x0010)
#define RCERH_3 (0x0008)
#define RCERH_2 (0x0004)
#define RCERH_1 (0x0002)
#define RCERH_0 (0x0001)

// MCBSPLP_XCERG_REG
#define XCERG_F (0x8000)
#define XCERG_E (0x4000)
#define XCERG_D (0x2000)
#define XCERG_C (0x1000)
#define XCERG_B (0x0800)
#define XCERG_A (0x0400)
#define XCERG_9 (0x0200)
#define XCERG_8 (0x0100)
#define XCERG_7 (0x0080)
#define XCERG_6 (0x0040)
#define XCERG_5 (0x0020)
#define XCERG_4 (0x0010)
#define XCERG_3 (0x0008)
#define XCERG_2 (0x0004)
#define XCERG_1 (0x0002)
#define XCERG_0 (0x0001)

// MCBSPLP_XCERH_REG
#define XCERH_F (0x8000)
#define XCERH_E (0x4000)
#define XCERH_D (0x2000)
#define XCERH_C (0x1000)
#define XCERH_B (0x0800)
#define XCERH_A (0x0400)
#define XCERH_9 (0x0200)
#define XCERH_8 (0x0100)
#define XCERH_7 (0x0080)
#define XCERH_6 (0x0040)
#define XCERH_5 (0x0020)
#define XCERH_4 (0x0010)
#define XCERH_3 (0x0008)
#define XCERH_2 (0x0004)
#define XCERH_1 (0x0002)
#define XCERH_0 (0x0001)

typedef struct
{
/*UINT32 u32REVNB;
UINT32 u32Reserved004;
UINT32 u32Reserved008;
UINT32 u32Reserved00C;
UINT32 u32SYSCONFIG;
UINT32 u32Reserved014;
UINT32 u32Reserved018;
UINT32 u32Reserved01C;
UINT32 u32IRQSTATUS_RAW_;
//UINT32 u32IRQSTATUS;
UINT32 u32IRQENABLE_SET;
UINT32 u32IRQENABLE_CLR;
UINT32 u32DMARXENABLE_SET;
UINT32 u32DMATXENABLE_SET;
UINT32 u32DMARXENABLE_CLR;
UINT32 u32DMATXENABLE_CLR;
UINT32 u32DMARXWAKE_EN;
UINT32 u32DMATXWAKE_EN;
*/
UINT32 u32DRR_REG;
UINT32 u32DXR_REG;
UINT32 u32SPCR2_REG;
UINT32 u32SPCR1_REG;
UINT32 u32RCR2_REG;
UINT32 u32RCR1_REG;
UINT32 u32XCR2_REG;
UINT32 u32XCR1_REG;
UINT32 u32SRGR2_REG;
UINT32 u32SRGR1_REG;
UINT32 u32MCR2_REG;
UINT32 u32MCR1_REG;
UINT32 u32RCERA_REG;
UINT32 u32RCERB_REG;
UINT32 u32XCERA_REG;
UINT32 u32XCERB_REG;
UINT32 u32PCR_REG;
UINT32 u32RCERC_REG;
UINT32 u32RCERD_REG;
UINT32 u32XCERC_REG;
UINT32 u32XCERD_REG;
UINT32 u32RCERE_REG;
UINT32 u32RCERF_REG;
UINT32 u32XCERE_REG;
UINT32 u32XCERF_REG;
UINT32 u32RCERG_REG;
UINT32 u32RCERH_REG;
UINT32 u32XCERG_REG;
UINT32 u32XCERH_REG;
UINT32 u32REV_REG;
UINT32 u32RINTCLR_REG;
UINT32 u32XINTCLR_REG;
UINT32 u32ROVFLCLR_REG;
UINT32 u32SYSCONFIG_REG;
UINT32 u32THRSH2_REG;
UINT32 u32THRSH1_REG;
UINT32 u32IRQSTATUS;
UINT32 u32IRQENABLE;
UINT32 u32WAKEUP_EN;
UINT32 u32XCCR_REG;
UINT32 u32RCCR_REG;
UINT32 u32XBUFFSTAT_REG;
UINT32 u32RBUFFSTAT_REG;
UINT32 u32STATUS_REG;

}_DM814x_MCBSP_REGS_, *DM814x_MCBSP_REGS;

#ifdef __cplusplus
} /* End of extern C */
#endif /* #ifdef __cplusplus */

#endif /* End of _DM814x_McBSP_H_ */

//c file//

#include "stdio.h"
#include "DM814x_EVM.h"
#include "mcbsp.h"
#include "DM814x.h"
#define CM_ALWON_MCBSP_CLKCTRL  0x4818154C

void init_mcbsp_loopback(DM814x_MCBSP_REGS stMcBspRegs)
{
	  WR_MEM_32(CM_ALWON_MCBSP_CLKCTRL,0x2);
	  while (RD_MEM_32(CM_ALWON_MCBSP_CLKCTRL)!=0x2);
	    int j=0, k=0, n=4, i=0;
       unsigned int errorflag = 0;
	//uint32_t buff;
	//initializing Mcbsp Module//
	stMcBspRegs = (DM814x_MCBSP_REGS) MCBSP_BASE_ADDRESS ;
	while (stMcBspRegs -> u32SPCR2_REG & 0x00C00000 );

	stMcBspRegs -> u32SPCR2_REG    = 0x0000;
	stMcBspRegs -> u32SPCR1_REG    = 0x0000;

	for(j=0;j<(2*100);j++) //wait for atleast 2clkgs
		     {};
	//mcbsp configuration registers//


	stMcBspRegs -> u32SPCR2_REG    = 0x00000001;//set spcr2-xrst bit 1//transmitter is enabled
	stMcBspRegs -> u32SPCR1_REG    = 0x00000001;//set spcr1-rrst bit 1//receiver is ready


	//stMcBspRegs -> u32SPCR2_REG    = 0x00008000; //SPCR : ALB
	stMcBspRegs -> u32SPCR1_REG    = 0x00008000; //SPCR : ALB
	stMcBspRegs -> u32DXR_REG      = 0xAAAAAAAA; //SPCR : ALB

	//WR_MEM_32(MCBSP_DXR_REG_OFFSET,0xAAAAAAAA);//writing data to dxr register
	stMcBspRegs -> u32SPCR1_REG    = 0x00004001; //SPCR : ALB nd receiver is enabled

	for(j=0;j<(2*100);j++) //wait for atleast 2clks for receiver nd transmitter to become active
		{};
	stMcBspRegs -> u32SPCR2_REG    = 0x00000041;//transmitter enabled and frame synchronization

     //reset initialization procedure for the sample rate generator SRG//
	//stMcBspRegs -> u32XCCR_REG     = 0x00000010;
	stMcBspRegs -> u32SPCR2_REG    = 0x00000061; //SRG enabled,transmitter enabled,frame synchronized
	for(j=0;j<(2*100);j++) //wait for atleast 2clks for receiver nd transmitter to become active
			{};

	stMcBspRegs -> u32RCR2_REG     = 0x00000005; //RCR :32bits ,receive frame word length 2
	stMcBspRegs -> u32RCR1_REG     = 0x00000005; //RCR :32bits ,receive frame word length 1

	stMcBspRegs -> u32XCR2_REG     = 0x00000005; //XCR :32bits , xmit frame word length   2
	stMcBspRegs -> u32XCR1_REG     = 0x00000005; //XCR :32bits , xmit frame word length   1

	stMcBspRegs -> u32SRGR2_REG    = 0x00001000; //SRGR :CLKSM/SCLKME-1/0(INT), FSGM-DXRtoXSR frame, FPER-DC, FWID-DC, CLKGDV-FF


	stMcBspRegs -> u32PCR_REG      = 0x00000040;//PCR: FSXM-1(INT), FSRM-1(INTT), CLKXM-1(INT), CLKRM-0(driven by CLKXM in DLB)
	stMcBspRegs -> u32SPCR2_REG    = 0x00000061;


	//RX configuration//
	stMcBspRegs -> u32SPCR1_REG    = 0x00008000; //SPCR1 : ALB enabled
	stMcBspRegs -> u32XCCR_REG     = 0x00000010; //xccr  : DLB enabled
	stMcBspRegs -> u32RCR2_REG     = 0x00000005; //RCR :32bits ,receive frame word length 2
	stMcBspRegs -> u32RCR1_REG     = 0x00000005; //RCR :32bits ,receive frame word length 1

	//tx configuration
	stMcBspRegs -> u32SPCR1_REG    = 0x00008000; //SPCR1 : ALB enabled
	stMcBspRegs -> u32XCCR_REG     = 0x00000010; //xccr  : DLB enabled
	stMcBspRegs -> u32XCR2_REG     = 0x00000005; //XCR :32bits , xmit frame word length   2
	stMcBspRegs -> u32XCR1_REG     = 0x00000005; //XCR :32bits , xmit frame word length   1
	stMcBspRegs -> u32SRGR2_REG    = 0x000000FF; //setting the sample rate generator clock
	stMcBspRegs -> u32PCR_REG      = 0x00000040;
	//initialization of transmit values and array and received values//
//	for(k=0;k < n; k++)
//	{
		//initialize the array of received values to all 0s//

           //[k]=0
       //  *(unsigned int *)MCBSP_RBUFFSTAT_REG_OFFSET=0;
       //  *(unsigned int *)MCBSP_XBUFFSTAT_REG_OFFSET=0;
	// *(unsigned int *)MCBSP_RBUFFSTAT_REG_OFFSET[k]=0;
    // *(unsigned int *)MCBSP_XBUFFSTAT_REG_OFFSET[k]=k+1;

        //stMcBspRegs -> u32RBUFFSTAT_REG[k]=0; //clear receive buffer
		//stMcBspRegs -> u32XBUFFSTAT_REG[k]=k+1; //fill in dummy data

//	}

	//stMcBspRegs ->	u32SPCR2_REG = 0x00400000; //SPCR : GRST-on
	//stMcBspRegs ->	u32SPCR1_REG = 0x00400000;

	for(j=0;j<(2*100);j++) //wait for atleast 2clkgs
	     {};

/*	stMcBspRegs ->	u32SPCR2_REG = 0x00800000; //SPCR:FRST ON
	stMcBspRegs ->	u32SPCR1_REG = 0x00800000;

	stMcBspRegs ->	u32SPCR2_REG = 0x00000001; //SPCR :RRST ON
	stMcBspRegs ->	u32SPCR1_REG = 0x00000001;

	stMcBspRegs ->	u32SPCR2_REG = 0x00010000; //SPCR :XRST ON
	stMcBspRegs ->	u32SPCR1_REG = 0x00010000;
	stMcBspRegs -> u32XCCR_REG   = 0x00000010; */

	for (j=0;j<n;j++)

	{

	//poll for XRDY flag to acknowledge transmitter is ready//
		while(!(stMcBspRegs->u32SPCR2_REG & 0x00000002) == 0x00000002);


	//	while ((stMcBspRegs->u32SPCR2_REG & 0x00020000) != 0x00020000);
	//	while ((stMcBspRegs->u32SPCR1_REG & 0x00020000) != 0x00020000);
		// if( *(unsigned int *) MCBSP_XCCR_REG_OFFSET  ==  0x00000010 )

		if( *(unsigned int *) MCBSP_SPCR1_REG_OFFSET  == 0x00008000)
		 {
			 WR_MEM_32(MCBSP_DXR_REG_OFFSET,0xAAAAAAAA);
			 RD_MEM_32(MCBSP_DRR_REG_OFFSET);
	  if (*(unsigned int *) MCBSP_DRR_REG_OFFSET== *(unsigned int *) MCBSP_DXR_REG_OFFSET)
		  printf("\n pass \n");
	  else
		  printf("\n fail \n");
		 }

	*(unsigned int *)MCBSP_DXR_REG_OFFSET = *(unsigned int *)MCBSP_XBUFFSTAT_REG_OFFSET;

	//*(unsigned int *)MCBSP_DXR_REG_OFFSET = *(unsigned int *) (MCBSP_XBUFFSTAT_REG_OFFSET + j*4);

	//	stMcBspRegs -> u32DXR_REG = stMcBspRegs ->u32XBUFFSTAT_REG[j]; //DXR WRITE  [j]

   //poll for RRDY flag to acknowledge receiver is ready//

	while(!(stMcBspRegs->u32SPCR1_REG & 0x00000002) == 0x00000002);

	//while ((stMcBspRegs->u32SPCR2_REG & 0x00000002) != 0x00000002);
	//while ((stMcBspRegs->u32SPCR1_REG & 0x00000002) != 0x00000002);
	*(unsigned int *)MCBSP_RBUFFSTAT_REG_OFFSET  = *(unsigned int *)MCBSP_DRR_REG_OFFSET;
//	*(unsigned int *)MCBSP_RBUFFSTAT_REG_OFFSET[j]  = *(unsigned int *)MCBSP_DRR_REG_OFFSET[j];



	//stMcBspRegs ->	u32RBUFFSTAT_REG[j]=stMcBspRegs->u32DRR_REG; //DDR READ [j]
	}

	//compare tx and rx buffers//
	for (i=0;i<n;i++)
	{
	if (*(unsigned int *)MCBSP_RBUFFSTAT_REG_OFFSET != *(unsigned int *)MCBSP_XBUFFSTAT_REG_OFFSET)
//	if (*(unsigned int *)MCBSP_RBUFFSTAT_REG_OFFSET[i] != *(unsigned int *)MCBSP_XBUFFSTAT_REG_OFFSET[i])

  //  if (stMcBspRegs ->u32RBUFFSTAT_REG[i] != stMcBspRegs ->u32XBUFFSTAT_REG[i])
    {
     errorflag++;
     break;
	}
	}

	//check for test fail//
	if(errorflag != 0)
	 {
		printf( "*\n fail  *\n");
	 }
	else
	{
		printf("*\n pass *\n");
	 }
}

over 9 years ago

0 Pavel Botev over 9 years ago

TI__Guru**** 170625 points

Hi Tariq,

The McBSP base address is 0x47000000. The McBSP registers addresses listed in DM814x datasheet, Table 8-80 are correct.

Beside CM_ALWON_MCBSP_CLKCTRL registers, there are few more McBSP related registers at device level that you might check:

- McBSP_UART_CLKSRC/0x481C52D8 [2:0] McBSP_CLKS_SOURCE - if you supply the McBSP with clock from the PRCM, make sure this bits are 0x0

- CM_AUDIOCLK_MCBSP_CLKSEL/0x48180388 [1:0] CLKSEL - select the sysclk you want to use

- AUD_CTRL/0x4814064C - this register is used for loopback

Note also that you might need to open the McBSP FW before starting to program McBSP registers, see gel file PG2.1_Centaurus_20Mhz_Si.gel

#define MCBSP_FW 0x47C2E088

OpenFireWall(){

WR_MEM_32(MCBSP_FW, NETRA_TEST_DEVICE_FW_VAL);

The gel file is attached PG2.1_Centaurus_20Mhz_Si.gel

BR
Pavel

0 Muhammad Tariq over 9 years ago in reply to Pavel Botev

Intellectual 320 points

hi pavel

thanks for the pointers

I have configured the following registers as you asked for but now nothing is changing ,i used hardcoded as well as gel file to initialize the clks though clocks are configured as desired but there is no change in mcbsp module registers.

i am attaching the modified version of a code ,kindly see if am missing something again plus i have changed the base address back to 47000000 as well

#include "stdio.h"
#include "DM814x_EVM.h"
#include "mcbsp.h"
#include "DM814x.h"
#define CM_ALWON_MCBSP_CLKCTRL        0x4818154C
#define McBSP_UART_CLKSRC             0x481C52D8  //CM_AUDIOCLK_MCBSP
#define CM_AUDIOCLK_McBSP_CLKSEL      0x48180388  //clk sel  0x00 for sysclk 20
#define AUD_CTRL                      0x4814064C  //loopback control for mcbsp
#define MCBSP_FW                      0x47C2E088
#define NETRA_TEST_DEVICE_FW_VAL      0xFFFFFFFF


OpenFireWall()
{


    WR_MEM_32(MCBSP_FW,NETRA_TEST_DEVICE_FW_VAL);


}

void init_mcbsp_loopback(DM814x_MCBSP_REGS stMcBspRegs)
{
	  WR_MEM_32(CM_ALWON_MCBSP_CLKCTRL,0x2);
	  while (RD_MEM_32(CM_ALWON_MCBSP_CLKCTRL)!=0x2);

	  WR_MEM_32(McBSP_UART_CLKSRC,0x0);
	  while (RD_MEM_32(McBSP_UART_CLKSRC)!=0x0);

	  WR_MEM_32(CM_AUDIOCLK_McBSP_CLKSEL,0x0);
	  while (RD_MEM_32(CM_AUDIOCLK_McBSP_CLKSEL)!=0x0);

	  WR_MEM_32(AUD_CTRL,0x3);        //McBSP FSX and CLKX Loopback enable
	  while (RD_MEM_32(AUD_CTRL)!=0x3);







	    int j=0, k=0, n=4, i=0;
       unsigned int errorflag = 0;
	//uint32_t buff;
	//initializing Mcbsp Module//
	stMcBspRegs = (DM814x_MCBSP_REGS) MCBSP_BASE_ADDRESS ;
	while (stMcBspRegs -> u32SPCR2_REG & 0x00C00000 );

	stMcBspRegs -> u32SPCR2_REG    = 0x0000;
	stMcBspRegs -> u32SPCR1_REG    = 0x0000;

	for(j=0;j<(2*100);j++) //wait for atleast 2clkgs
		     {};
	//mcbsp configuration registers//


	stMcBspRegs -> u32SPCR2_REG    = 0x00000001;//set spcr2-xrst bit 1//transmitter is enabled
	stMcBspRegs -> u32SPCR1_REG    = 0x00000001;//set spcr1-rrst bit 1//receiver is ready


	//stMcBspRegs -> u32SPCR2_REG    = 0x00008000; //SPCR : ALB
	stMcBspRegs -> u32SPCR1_REG    = 0x00008000; //SPCR : ALB
	stMcBspRegs -> u32DXR_REG      = 0xAAAAAAAA; //SPCR : ALB

	//WR_MEM_32(MCBSP_DXR_REG_OFFSET,0xAAAAAAAA);//writing data to dxr register
	stMcBspRegs -> u32SPCR1_REG    = 0x00004001; //SPCR : ALB nd receiver is enabled

	for(j=0;j<(2*100);j++) //wait for atleast 2clks for receiver nd transmitter to become active
		{};
	stMcBspRegs -> u32SPCR2_REG    = 0x00000041;//transmitter enabled and frame synchronization

     //reset initialization procedure for the sample rate generator SRG//
	//stMcBspRegs -> u32XCCR_REG     = 0x00000010;
	stMcBspRegs -> u32SPCR2_REG    = 0x00000061; //SRG enabled,transmitter enabled,frame synchronized
	for(j=0;j<(2*100);j++) //wait for atleast 2clks for receiver nd transmitter to become active
			{};

	stMcBspRegs -> u32RCR2_REG     = 0x00000005; //RCR :32bits ,receive frame word length 2
	stMcBspRegs -> u32RCR1_REG     = 0x00000005; //RCR :32bits ,receive frame word length 1

	stMcBspRegs -> u32XCR2_REG     = 0x00000005; //XCR :32bits , xmit frame word length   2
	stMcBspRegs -> u32XCR1_REG     = 0x00000005; //XCR :32bits , xmit frame word length   1

	stMcBspRegs -> u32SRGR2_REG    = 0x00001000; //SRGR :CLKSM/SCLKME-1/0(INT), FSGM-DXRtoXSR frame, FPER-DC, FWID-DC, CLKGDV-FF


	stMcBspRegs -> u32PCR_REG      = 0x00000040;//PCR: FSXM-1(INT), FSRM-1(INTT), CLKXM-1(INT), CLKRM-0(driven by CLKXM in DLB)
	stMcBspRegs -> u32SPCR2_REG    = 0x00000061;


	//RX configuration//
	stMcBspRegs -> u32SPCR1_REG    = 0x00008000; //SPCR1 : ALB enabled
	stMcBspRegs -> u32XCCR_REG     = 0x00000010; //xccr  : DLB enabled
	stMcBspRegs -> u32RCR2_REG     = 0x00000005; //RCR :32bits ,receive frame word length 2
	stMcBspRegs -> u32RCR1_REG     = 0x00000005; //RCR :32bits ,receive frame word length 1

	//tx configuration
	stMcBspRegs -> u32SPCR1_REG    = 0x00008000; //SPCR1 : ALB enabled
	stMcBspRegs -> u32XCCR_REG     = 0x00000010; //xccr  : DLB enabled
	stMcBspRegs -> u32XCR2_REG     = 0x00000005; //XCR :32bits , xmit frame word length   2
	stMcBspRegs -> u32XCR1_REG     = 0x00000005; //XCR :32bits , xmit frame word length   1
	stMcBspRegs -> u32SRGR2_REG    = 0x000000FF; //setting the sample rate generator clock
	stMcBspRegs -> u32PCR_REG      = 0x00000040;
	//initialization of transmit values and array and received values//
//	for(k=0;k < n; k++)
//	{
		//initialize the array of received values to all 0s//

           //[k]=0
       //  *(unsigned int *)MCBSP_RBUFFSTAT_REG_OFFSET=0;
       //  *(unsigned int *)MCBSP_XBUFFSTAT_REG_OFFSET=0;
	// *(unsigned int *)MCBSP_RBUFFSTAT_REG_OFFSET[k]=0;
    // *(unsigned int *)MCBSP_XBUFFSTAT_REG_OFFSET[k]=k+1;

        //stMcBspRegs -> u32RBUFFSTAT_REG[k]=0; //clear receive buffer
		//stMcBspRegs -> u32XBUFFSTAT_REG[k]=k+1; //fill in dummy data

//	}

	//stMcBspRegs ->	u32SPCR2_REG = 0x00400000; //SPCR : GRST-on
	//stMcBspRegs ->	u32SPCR1_REG = 0x00400000;

	for(j=0;j<(2*100);j++) //wait for atleast 2clkgs
	     {};

/*	stMcBspRegs ->	u32SPCR2_REG = 0x00800000; //SPCR:FRST ON
	stMcBspRegs ->	u32SPCR1_REG = 0x00800000;

	stMcBspRegs ->	u32SPCR2_REG = 0x00000001; //SPCR :RRST ON
	stMcBspRegs ->	u32SPCR1_REG = 0x00000001;

	stMcBspRegs ->	u32SPCR2_REG = 0x00010000; //SPCR :XRST ON
	stMcBspRegs ->	u32SPCR1_REG = 0x00010000;
	stMcBspRegs -> u32XCCR_REG   = 0x00000010; */

	for (j=0;j<n;j++)

	{

	//poll for XRDY flag to acknowledge transmitter is ready//
		while(!(stMcBspRegs->u32SPCR2_REG & 0x00000002) == 0x00000002);


	//	while ((stMcBspRegs->u32SPCR2_REG & 0x00020000) != 0x00020000);
	//	while ((stMcBspRegs->u32SPCR1_REG & 0x00020000) != 0x00020000);
		// if( *(unsigned int *) MCBSP_XCCR_REG_OFFSET  ==  0x00000010 )

		if( *(unsigned int *) MCBSP_SPCR1_REG_OFFSET  == 0x00008000)
		 {
			 WR_MEM_32(MCBSP_DXR_REG_OFFSET,0xAAAAAAAA);
			 RD_MEM_32(MCBSP_DRR_REG_OFFSET);
	  if (*(unsigned int *) MCBSP_DRR_REG_OFFSET== *(unsigned int *) MCBSP_DXR_REG_OFFSET)
		  printf("\n pass \n");
	  else
		  printf("\n fail \n");
		 }

	*(unsigned int *)MCBSP_DXR_REG_OFFSET = *(unsigned int *)MCBSP_XBUFFSTAT_REG_OFFSET;

	//*(unsigned int *)MCBSP_DXR_REG_OFFSET = *(unsigned int *) (MCBSP_XBUFFSTAT_REG_OFFSET + j*4);

	//	stMcBspRegs -> u32DXR_REG = stMcBspRegs ->u32XBUFFSTAT_REG[j]; //DXR WRITE  [j]

   //poll for RRDY flag to acknowledge receiver is ready//

	while(!(stMcBspRegs->u32SPCR1_REG & 0x00000002) == 0x00000002);

	//while ((stMcBspRegs->u32SPCR2_REG & 0x00000002) != 0x00000002);
	//while ((stMcBspRegs->u32SPCR1_REG & 0x00000002) != 0x00000002);
	*(unsigned int *)MCBSP_RBUFFSTAT_REG_OFFSET  = *(unsigned int *)MCBSP_DRR_REG_OFFSET;
//	*(unsigned int *)MCBSP_RBUFFSTAT_REG_OFFSET[j]  = *(unsigned int *)MCBSP_DRR_REG_OFFSET[j];



	//stMcBspRegs ->	u32RBUFFSTAT_REG[j]=stMcBspRegs->u32DRR_REG; //DDR READ [j]
	}

	//compare tx and rx buffers//
	for (i=0;i<n;i++)
	{
	if (*(unsigned int *)MCBSP_RBUFFSTAT_REG_OFFSET != *(unsigned int *)MCBSP_XBUFFSTAT_REG_OFFSET)
//	if (*(unsigned int *)MCBSP_RBUFFSTAT_REG_OFFSET[i] != *(unsigned int *)MCBSP_XBUFFSTAT_REG_OFFSET[i])

  //  if (stMcBspRegs ->u32RBUFFSTAT_REG[i] != stMcBspRegs ->u32XBUFFSTAT_REG[i])
    {
     errorflag++;
     break;
	}
	}

	//check for test fail//
	if(errorflag != 0)
	 {
		printf( "*\n fail  *\n");
	 }
	else
	{
		printf("*\n pass *\n");
	 }
}

0 Pavel Botev over 9 years ago

TI__Guru**** 170625 points

Tariq,

Muhammad Tariq said:
My main problem is that if i am setting a specific register by writing some values ,it is not writing there but writing somewhere else and in few registers which are completely writeable but i am not able to write them.

Can you provide more details regarding your main issue? Which specific register, what values you want to write there? Where these values are written?

Do you want to make internal loopback or external loopback? If external, also McBSP pins should be setup.

Can you also start the McBSP init procedure with initiating software reset from the SYSCONFIG_REG[1] SOFTRESET bit?

BR
Pavel

0 Muhammad Tariq over 9 years ago in reply to Pavel Botev

Intellectual 320 points

yes
for initializing mcbsp module i am writing values to registers such as spcr2(47000110) , spcr1(47000114) etc etc but the values were written to some other registers and for some registers like DXR(47000100) i am not able to write anything ,same is the case for Analog loopback bit spcr1[15].But this behaviour was shown when i was implenting without setting up the registers you mentioned earlier but after setting up those clocks ,it is not writing anything.
and i am trying to implement internal loopback therefore no need to setup the pin configuration.

0 Pavel Botev over 9 years ago in reply to Muhammad Tariq

TI__Guru**** 170625 points

Tariq,

Muhammad Tariq said:
But this behaviour was shown when i was implenting without setting up the registers you mentioned earlier but after setting up those clocks ,it is not writing anything.

If you remove AUD_CTRL init at the beginning and leave the rest of the registers, will you be able to write the values again?
Seems like this AUD_CTRL register should be program at later stage, see section 17.2.8.5.4 Enable/Disable the Synchronous Transmit-Receive Mode

Can you also start the McBSP init procedure with initiating software reset from the SYSCONFIG_REG[1] SOFTRESET bit?

BR
Pavel

0 Pavel Botev over 9 years ago in reply to Muhammad Tariq

TI__Guru**** 170625 points

Tariq,

Muhammad Tariq said:
#define MCBSP_FW 0x47C2E088
#define NETRA_TEST_DEVICE_FW_VAL 0xFFFFFFFF

OpenFireWall() { WR_MEM_32(MCBSP_FW,NETRA_TEST_DEVICE_FW_VAL); }

I would recommend to apply the below code for the firewall:

#define CTRL_MODULE_BASE_ADDR 0x48140000
#define CONTROL_STATUS (CTRL_MODULE_BASE_ADDR + 0x040)

#define MCBSP_FW                      0x47C2E088
#define NETRA_TEST_DEVICE_FW_VAL      0xFFFFFFFF

OpenFireWall()
{

if( (RD_MEM_32(CONTROL_STATUS) & 0x700) ==0) {
GEL_TextOut("\tDevice type is TEST \n","Output",1,1,1);
GEL_TextOut("\tOpen the Firewall for public \n","Output",1,1,1);

WR_MEM_32(MCBSP_FW, NETRA_TEST_DEVICE_FW_VAL);

}
else if( (RD_MEM_32(CONTROL_STATUS) & 0x700) ==0x300) {
GEL_TextOut("\tDevice type is GP \n","Output",1,1,1);
}
}

Try also to setup the McBSP memory map, like in DM816x gel file (attached):

/* ------------------------------------------------------------------------ *
*                                                                          *
* Setup_Memory_Map( )                                                     *
*      Setup the Memory Map for the Cortex A8                              *
*                                                                          *
* ------------------------------------------------------------------------ */

Setup_Memory_Map( )
{
    GEL_MapOn( );
    GEL_MapReset( );

    /* Device Memory Map */

    /* L3 Memory Map */

GEL_MapAddStr( 0x47000000, 0, 0x00400000, "R|W|AS4", 0 ); // McBSP

GEL_MapAddStr( 0x47C2E000, 0, 0x00001000, "R|W|AS4", 0 ); // McBSP Firewall-Module

GEL_MapAddStr( 0x47C2F000, 0, 0x00001000, "R|W|AS4", 0 ); // McBSP Firewall-L4 interconnect

}

evm816x.gel

0 Muhammad Tariq over 9 years ago in reply to Pavel Botev

Intellectual 320 points

thanks for the help
i have tried as well with sysconfig nd removing of aud_ctrl and configuring at the right place but nothing changed .also tried your way for firewall still it doesnt work.Even i am not able to write anything to DXR(R/W) reg 0x47000100.the value at this register is fixed .not changing at all not by writing to it via code or manually via memory browser.

0 Pavel Botev over 9 years ago in reply to Muhammad Tariq

TI__Guru**** 170625 points

Tariq,

There are two loopback modes in McBSP:

1. analog loopback - this includes the McBSP pins and AUD_CTRL register
2. digital loopback - this is internal, no pins

So you should align your code for digital loopback (as you state you do not want to involve the McBSP pins here). Remove also the AUD_CTRL register settings. Config only for digital loopback, not both.

Make sure you follow the below sequence:

1. make softreset through the SYSCONFIG register and wait untill reset is complete
2. Program SPCR1[0]RRST = 0, SPCR2[0] XRST = 0, SPCR2[7] FRST = 0, apply mask, program only these bits, not the whole registers
3. Program config registers (SPCR1/2, PCR, RCR1/2, XCR1/2, SRGR1/2)
4. wait for two clock cycles
5. SPCR[0] RRST = 1, SPCR2[0] XRST = 1, apply mask, program only these bits, not the whole registers
6. check SPCR2[1] XRDY == 1
6. write to DXR_REG
7. set SPCR2[7] FRST = 1
8. wait for two clock cycles
....

BR
Pavel

0 ranchu over 8 years ago in reply to Pavel Botev

Guru 20755 points

Is it resolved ?
Is there any example - whatsoever (Linux or other) - for mcbsp ?

Thank you,
Ran

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