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How to handle the interrupts and traps about 66AK2L06?

chas chen
Prodigy 240 points
Other Parts Discussed in Thread: 66AK2L06

Hi all,

       I have a questions about the multiple errors of 66AK2L06's L2 Cache. It is shown that the dsp would enter a trap when uncorrectable errors happen in L2 cache.

In fact, there is no trap or interrupt service routines. How shoud I do to add the ISR in my project? BTW, I don't fina *.asm file which defines interrupt vector table yet.

Are there many differences between 6713 and 66AK2L06. The poeject in CCS 6.1 don't give any example program.

Any help is appreciated.

Chas

  • 0
    TI__Mastermind 43955 points

    Hi Chas,

    chas said:
      I have a questions about the multiple errors of 66AK2L06's L2 Cache. It is shown that the dsp would enter a trap when uncorrectable errors happen in L2 cache.

    Would you please make us understand how did you come across those multiple errors at L2 cache? I mean to ask, what did you do or what programs you run on 66AK2L06 which resulted on errors? Did you run any standard TI package examples /demos?

    chas said:
    In fact, there is no trap or interrupt service routines. How shoud I do to add the ISR in my project? BTW, I don't fina *.asm file which defines interrupt vector table yet.

    If you are looking for any example for INTC, you can refer to the TI released software package, "pdk_keystone2_3_01_04_07" which is part of MCSDK version 3.1.4.7. After installing this package, you will find the source at path :"~\pdk_keystone2_3_01_04_07\packages\ti\csl\src\intc"

    chas said:
     Are there many differences between 6713 and 66AK2L06. The poeject in CCS 6.1 don't give any example program.

    C6713 is the Single core processor which has one highest-Performance Floating-Point Digital Signal Processor (DSP).

    The 66AK2L06 KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture which has Four TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
    DSP Core and Two ARM® Cortex®-A15 MPCore™ Processors
    at Up to 1.2 GHz

    --------------------------

  • 0
    TI__Guru* 81335 points

    Hi Chas Chen,

    In keystone devices, you can handle interrupts using CSL or SYS/BIOS API's. Please refer below wiki page for more information.

    http://processors.wiki.ti.com/index.php/Configuring_Interrupts_on_Keystone_Devices

    As Shankari pointed out above, there are CSL and SYS/BIOS based  interrupt examples available in MCSDK under PDK directory.

    Thank you.

  • 0 in reply to Raja
    Prodigy 240 points
    Hi Rajasekaran,
    Thanks for your reply.
    I will review the link you give. Then, I wii give a reply.
    Thanks

    Chas
  • 0 in reply to Shankari G
    Prodigy 240 points
    Hi Shankari,
    Very thanks for your help.
    Actually, I did't run a standard TI package examples.
    In our applicatiom, realability is a critical target. So, the EDC is enable. We need to know how to do when multiple errors occur in L2 cache.
    Several years ago, I developed a 6713 DSP. In a 6713 project, there are interrupt vector tables (vecetor.asm file)and ISR. The programmer just design the ISR to control what will to do when the interrupt occurs.

    So, my question is where is interrupt vector tables (vecetor.asm file)and ISR in 66AK2L06 project(CCS 6.1). Of cource, I will review the TI released software package to study how to control the dsp's operation when multiple errors occur.

    Thanks for your tips.

    Chas