when I use AIF to transfer packets, butalways find some packets lost

HI Liangzhan Xie ,
Due to weekend the responses will be delayed. We will get back to you as soon as possible. Thank you for your patience.

Hello,

A few questions:

1) what version of the PDK are you using?

2) Are you running the LTE test in ti/drv/aif2/test/lte?  If not, do any of the LLD tests work?

3) Are you running a GEL file to initialize clock and memory speeds? (e.g. C:\ti\ccsv6\ccs_base\emulation\boards\evmc6670l\gel\evmc6670l.gel)

If this is the standard LLD test, it should work given the board configuration (from the gel) is correct.

Hello db_woodall,
Thanks for your replay.
1)The CCS is CCS5.5,my C6670 EVM board is TMDSEVM6670LE Rev4.0,the AIF_LTE_FDD example project is based on CSL and come from K1_STK_v1.1.The main purpose of the K1_STK_v1.1 is to help hardware debug including new board bring-up and failure analysis. he STK also measures the performance of most modules in the KeyStone device.
2)I don't run the LTE test in ti/drv/aif2/test/lte.The AIF_LTE_FDD which is from K1_STK_v1.1 is implemented in two layers, the first layer is:main()function that are test functions for different test cases;the second layer is low level hardware configuration and driver which is based on CSL.
3)I don't run a GEL file to initialize clock and memory speeds.

If it is necessary,I can provide the AIF_LTE_FDD to you.

I am not familiar with this test (AIF_LTE_FDD). I see from the output that it is a loopback test, so you are probably not depending on a connection to another device for this test. So assuming that the test code has not been modified, it should pass on a properly configured and working board (which is why I asked if the PDK's AIF2 example tests (in ti/drv/aif2/test) also pass).

You can upload the test (to this thread) and I will run it on my 6618.  Also, you can try running a gel first (see below), and also try running a few of the PDK tests.

Below is the output of the default CCS GEL file loaded for a TCI6618 EVM. It is found in C:\ti\ccsv6\ccs_base\emulation\boards\evmc6670l\gel. Once you enter CCS debug mode by launching the target configuration, there should be a "GEL Files" window/tab (next to the Scripting Console and Target Configuration tabs). Right click in the window and select "Load GEL". Then connect to C66xx_0. This will run the gel and produce the following:

C66xx_0: GEL Output: Setup_Memory_Map...

C66xx_0: GEL Output: Setup_Memory_Map... Done.

C66xx_0: GEL Output: Global Default Setup...

C66xx_0: GEL Output: C6670L GEL file Ver is 2.005

C66xx_0: GEL Output: Setup Cache...

C66xx_0: GEL Output: L1P = 32K

C66xx_0: GEL Output: L1D = 32K

C66xx_0: GEL Output: L2 = ALL SRAM

C66xx_0: GEL Output: Setup Cache... Done.

C66xx_0: GEL Output: Main PLL (PLL1) Setup ...

C66xx_0: GEL Output: PLL in Bypass ...

C66xx_0: GEL Output: PLL1 Setup for DSP @ 983.0 MHz.

C66xx_0: GEL Output: SYSCLK2 = 327.6667 MHz, SYSCLK5 = 196.6 MHz.

C66xx_0: GEL Output: SYSCLK8 = 15.35938 MHz.

C66xx_0: GEL Output: PLL1 Setup... Done.

C66xx_0: GEL Output: Power on all PSC modules and DSP domains...

C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.

C66xx_0: GEL Output: PA PLL (PLL3) Setup ...

C66xx_0: GEL Output: PA PLL Setup... Done.

C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...

C66xx_0: GEL Output: DDR3 PLL Setup... Done.

C66xx_0: GEL Output: DDR begin (1333 auto)

C66xx_0: 2: XMC setup complete.

C66xx_0: GEL Output:

DDR3 initialization is complete.

C66xx_0: GEL Output: DDR done

C66xx_0: GEL Output: DDR3 memory test... Started

C66xx_0: GEL Output: DDR3 memory test... Passed

C66xx_0: GEL Output: PLL and DDR Initialization completed(0) ...

C66xx_0: GEL Output: configSGMIISerdes Setup... Begin

C66xx_0: GEL Output:

SGMII SERDES has been configured.

C66xx_0: GEL Output: Set Board and DSP IO/Timers Pins...

C66xx_0: GEL Output: Set Board and DSP IO/Timers Pins... Done.

C66xx_0: GEL Output: Configuring CPSW ...

C66xx_0: GEL Output: Configuring CPSW ...Done

C66xx_0: GEL Output: Global Default Setup... Done.

C66xx_0: GEL Output: Setup_Memory_Map...

C66xx_0: GEL Output: Setup_Memory_Map... Done.

C66xx_0: GEL Output: Global Default Setup...

C66xx_0: GEL Output: C6670L GEL file Ver is 2.005

C66xx_0: GEL Output: Setup Cache...

C66xx_0: GEL Output: L1P = 32K

C66xx_0: GEL Output: L1D = 32K

C66xx_0: GEL Output: L2 = ALL SRAM

C66xx_0: GEL Output: Setup Cache... Done.

C66xx_0: GEL Output: Main PLL (PLL1) Setup ...

C66xx_0: GEL Output: PLL in Bypass ...

C66xx_0: GEL Output: PLL1 Setup for DSP @ 983.0 MHz.

C66xx_0: GEL Output: SYSCLK2 = 327.6667 MHz, SYSCLK5 = 196.6 MHz.

C66xx_0: GEL Output: SYSCLK8 = 15.35938 MHz.

C66xx_0: GEL Output: PLL1 Setup... Done.

C66xx_0: GEL Output: Power on all PSC modules and DSP domains...

C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.

C66xx_0: GEL Output: PA PLL (PLL3) Setup ...

C66xx_0: GEL Output: PA PLL Setup... Done.

C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...

C66xx_0: GEL Output: DDR3 PLL Setup... Done.

C66xx_0: GEL Output: DDR begin (1333 auto)

C66xx_0: 2: XMC setup complete.

C66xx_0: GEL Output:

DDR3 initialization is complete.

C66xx_0: GEL Output: DDR done

C66xx_0: GEL Output: DDR3 memory test... Started

C66xx_0: GEL Output: DDR3 memory test... Passed

C66xx_0: GEL Output: PLL and DDR Initialization completed(0) ...

C66xx_0: GEL Output: configSGMIISerdes Setup... Begin

C66xx_0: GEL Output:

SGMII SERDES has been configured.

C66xx_0: GEL Output: Set Board and DSP IO/Timers Pins...

C66xx_0: GEL Output: Set Board and DSP IO/Timers Pins... Done.

C66xx_0: GEL Output: Configuring CPSW ...

C66xx_0: GEL Output: Configuring CPSW ...Done

C66xx_0: GEL Output: Global Default Setup... Done.

Hello db_woodall,

The test is indeed loopback test.Also,the test code has not been modified.

I have uploaded the test 4478.AIF2_LTE_FDD.rar(to this thread) and you can  download and run it on your 6618EVM with some necessary modification.The test is the internal loopback test output on C6670 or TCI6614 EVM for CPRI mode of AIF2_LTE_FDD project.

I  found the gel of C6670 in C:\ti\ccsv6\ccs_base\emulation\boards\evmc6670l\gel. I also have run it as your description.Below is the output of the default CCS GEL file loaded for a C6670 EVM.

C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: C6670L GEL file Ver is 2.005
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K
C66xx_0: GEL Output: L1D = 32K
C66xx_0: GEL Output: L2 = ALL SRAM
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 983.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 327.6667 MHz, SYSCLK5 = 196.6 MHz.
C66xx_0: GEL Output: SYSCLK8 = 15.35938 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Security Accelerator disabled!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ...
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: 2: XMC setup complete.
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Passed
C66xx_0: GEL Output: PLL and DDR Initialization completed(0) ...
C66xx_0: GEL Output: configSGMIISerdes Setup... Begin
C66xx_0: GEL Output:
SGMII SERDES has been configured.
C66xx_0: GEL Output: Set Board and DSP IO/Timers Pins...
C66xx_0: GEL Output: Set Board and DSP IO/Timers Pins... Done.
C66xx_0: GEL Output: Configuring CPSW ...
C66xx_0: GEL Output: Configuring CPSW ...Done
C66xx_0: GEL Output: Global Default Setup... Done.

Then I reload my program to C6670 EVM ,the result is the same as before:

[C66xx_0] JTAG ID= 0x1b94102f. This is C6670/TCI6618 device, version variant = 1.
DEVSTAT= 0x00000001. little endian, No boot or EMIF16(NOR FLASH) or UART boot, PLL configuration implies the input clock for core is 50MHz.
SmartReflex VID= 63, required core voltage= 1.104V.
Die ID= 0x12010016, 0x0403e766, 0x80000000, 0x64f60022
Device speed grade = 1200MHz.
Enable Exception handling...
Initialize DSP main clock = 122.88MHz/29x236 = 999MHz
Initialize DDR speed = 66.67MHzx/1x20 = 1333.340MTS
=================AIF CPRI mode test for 2000 ms (200 frames, LTE FDD normal cyclic prefix)=================
link 0 runs at 8x rate, internal loopback test, LTE 20 MHz AxC, antenna data in AxC slot only
link 1 runs at 4x rate, internal loopback test, LTE 10 MHz AxC, antenna data in AxC slot only
link 2 runs at 2x rate, internal loopback test, LTE 5 MHz AxC, antenna data on AxC slot, generic data on control slot, generic packet size = 10240
link 3 runs at 4x rate, internal loopback test, generic data in AxC slot only, generic packet size = 10240
link 4 runs at 4x rate, internal loopback test, LTE 20 MHz AxC, antenna data in AxC slot only
link 5 runs at 4x rate, internal loopback test, LTE 20 MHz AxC, antenna data in AxC slot only
----------------runtime error/status interrupt log--------------
0 error/status interrupt EE_LK_STS_A0 happens at frame 0, slot/symbol 0, clock 15190
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
1 error/status interrupt EE_LK_STS_A0 happens at frame 1, slot/symbol 0, clock 603
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
2 error/status interrupt EE_LK_STS_B0 happens at frame 1, slot/symbol 0, clock 603
20 pe_ee_db_starve_err: Link-by-Link (Error), DB did not have antenna data for a AxC channel. Likely to occur if DMA was late.
3 error/status interrupt EE_LK_STS_A1 happens at frame 1, slot/symbol 0, clock 603
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
4 error/status interrupt EE_LK_STS_B1 happens at frame 1, slot/symbol 0, clock 603
20 pe_ee_db_starve_err: Link-by-Link (Error), DB did not have antenna data for a AxC channel. Likely to occur if DMA was late.
5 error/status interrupt EE_LK_STS_A2 happens at frame 1, slot/symbol 0, clock 603
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
6 error/status interrupt EE_LK_STS_A3 happens at frame 1, slot/symbol 0, clock 603
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
7 error/status interrupt EE_LK_STS_A4 happens at frame 1, slot/symbol 0, clock 603
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
8 error/status interrupt EE_LK_STS_A5 happens at frame 1, slot/symbol 0, clock 603
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
9 error/status interrupt EE_LK_STS_A0 happens at frame 2, slot/symbol 0, clock 16926
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
16 rm_ee_hfnsync_state_err: Per Link, CPRI only (Error): Indicates RX FSM in the hyperframe state that is, state ST3. (as defined by CPRI)
10 error/status interrupt EE_LK_STS_A1 happens at frame 2, slot/symbol 0, clock 16926
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
11 error/status interrupt EE_LK_STS_A2 happens at frame 2, slot/symbol 0, clock 16926
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
12 error/status interrupt EE_LK_STS_B2 happens at frame 2, slot/symbol 0, clock 16926
20 pe_ee_db_starve_err: Link-by-Link (Error), DB did not have antenna data for a AxC channel. Likely to occur if DMA was late.
13 error/status interrupt EE_LK_STS_A3 happens at frame 2, slot/symbol 0, clock 16926
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
14 error/status interrupt EE_LK_STS_A4 happens at frame 2, slot/symbol 0, clock 16926
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
15 error/status interrupt EE_LK_STS_B4 happens at frame 2, slot/symbol 0, clock 16926
20 pe_ee_db_starve_err: Link-by-Link (Error), DB did not have antenna data for a AxC channel. Likely to occur if DMA was late.
16 error/status interrupt EE_LK_STS_A5 happens at frame 2, slot/symbol 0, clock 16926
0 rm_ee_sync_status_change_err: Per Link (Information): Indicates that the RX state machine changed state
17 error/status interrupt EE_LK_STS_B5 happens at frame 2, slot/symbol 0, clock 16926
20 pe_ee_db_starve_err: Link-by-Link (Error), DB did not have antenna data for a AxC channel. Likely to occur if DMA was late.
------------------status when test complete---------------------
Ingress End Of Packet count = 336383
Egress End Of Packet count = 341009
AT PHYT Frame= 200, Clock= 1116
AT RADT Frame= 200, Symbol= 0, Clock= 343
----------------link 0 status----------------
captured PI value = 380
RM ST3 State FRAME_SYNC
TM FSM in FRAME_SYNC state
----------------link 1 status----------------
captured PI value = 485
RM ST3 State FRAME_SYNC
TM FSM in FRAME_SYNC state
----------------link 2 status----------------
captured PI value = 641
RM ST3 State FRAME_SYNC
TM FSM in FRAME_SYNC state
----------------link 3 status----------------
captured PI value = 735
RM ST3 State FRAME_SYNC
TM FSM in FRAME_SYNC state
----------------link 4 status----------------
captured PI value = 835
RM ST3 State FRAME_SYNC
TM FSM in FRAME_SYNC state
----------------link 5 status----------------
captured PI value = 936
RM ST3 State FRAME_SYNC
TM FSM in FRAME_SYNC state
AxC Channel 0 transfer 27720 packets, receive 27299 packets (27299 good, 0 bad), 239607232 bytes in CORE1_LL2, achieve 120 MB/s
AxC Channel 1 transfer 27720 packets, receive 27299 packets (27299 good, 0 bad), 239607232 bytes in CORE2_LL2, achieve 120 MB/s
AxC Channel 2 transfer 27720 packets, receive 27299 packets (27299 good, 0 bad), 239607232 bytes in CORE3_LL2, achieve 120 MB/s
Throughput of link 0 = 360 MB/s (81897 good packets, 0 bad packets)
AxC Channel 3 transfer 27720 packets, receive 27299 packets (27299 good, 0 bad), 119803616 bytes in SL2, achieve 60 MB/s
AxC Channel 4 transfer 27720 packets, receive 27299 packets (27299 good, 0 bad), 119803616 bytes in SL2, achieve 60 MB/s
Throughput of link 1 = 120 MB/s (54598 good packets, 0 bad packets)
AxC Channel 5 transfer 27720 packets, receive 27299 packets (27299 good, 0 bad), 59901808 bytes in SL2, achieve 30 MB/s
AxC Channel 6 transfer 27720 packets, receive 27299 packets (27299 good, 0 bad), 59901808 bytes in SL2, achieve 30 MB/s
generic Channel 7 transfer 1010 packets, receive 1005 packets (1005 good, 0 bad), 10291200 bytes in SL2, achieve 5 MB/s
Throughput of link 2 = 65 MB/s (55603 good packets, 0 bad packets)
generic Channel 8 transfer 17546 packets, receive 17541 packets (17541 good, 0 bad), 179619840 bytes in CORE1_LL2, achieve 90 MB/s
generic Channel 9 transfer 17546 packets, receive 17541 packets (17541 good, 0 bad), 179619840 bytes in CORE2_LL2, achieve 90 MB/s
Throughput of link 3 = 180 MB/s (35082 good packets, 0 bad packets)
AxC Channel 10 transfer 27720 packets, receive 27299 packets (27299 good, 0 bad), 239607232 bytes in CORE3_LL2, achieve 120 MB/s
AxC Channel 11 transfer 27720 packets, receive 27299 packets (27299 good, 0 bad), 239607232 bytes in SL2, achieve 120 MB/s
Throughput of link 4 = 240 MB/s (54598 good packets, 0 bad packets)
AxC Channel 12 transfer 27720 packets, receive 27299 packets (27299 good, 0 bad), 239607232 bytes in SL2, achieve 120 MB/s
AxC Channel 13 transfer 27720 packets, receive 27299 packets (27299 good, 0 bad), 239607232 bytes in SL2, achieve 120 MB/s
Throughput of link 5 = 240 MB/s (54598 good packets, 0 bad packets)
Total throughput of AIF = 1205 MB/s (336376 good packets, 0 bad packets)

But I also have no idea that the packets received is not equal to the packets transported.

Hello,

I ran the .out file from your tar and it gave very similar results to your output, only the received packet counts were off by 1 or 2.

This test was written by one of our FAEs, but is not part of the official MCSDK/PDK releases. It is not written to use the PDK's LLDs (AIF2, QMSS, CPPI, etc), but directly calls the CSL library, and so is not something we can support.  This test was apparently written to use AIF2 to send data back and forth between two C6670's on a dual-device board, and secondarily will loopback data for a single C6670 device.  It is possible there is a compile flag that needs to be set, a clock or timer needs to be set differently, etc. Difficult to say without spending time to debug it.

I would recommend running a few of the PDK's AIF2 example programs.  If you plan to use a working test program as a starting point for your application, I highly recommend using one of the PDK examples that utilize the various LLDs.

Hello db_woodall,
Thanks for your reply,I will try as your recommendation.

Hello db_woodall,
The BIOS MCSDK 2.0 User Guide says that the LLD Users Guide in $(TI_PDK_C6670_INSTALL_DIR)\packages\ti\drv\aif2\docs\AIF2-c6670_usersguide.pdf.But I can't the AIF2-c6670_usersguide.pdf in the location C:\ti\pdk_C6670_1_1_2_6\packages\ti\drv\aif2\docs of my computer.where can I find the LLD Users Guide? If you have it ,would you send one to me?

Hi,

For Keystone I devices, the primary user guide can be found here:

www.ti.com/.../sprugv7d.pdf

There is an additional user guide found in the /docs folder of more recent releases.  I will attach it here:

AIF2-c66xx_usersguide.pdf

Hello db_woodall,
Thank you very much!