Other Parts Discussed in Thread: SN65LVDS93
Hello:
I am working with our custom hardware that uses VOUT2 (not VOUT1 like the EVM) to output graphics to our LCD panel. Unfortunately, I am unable to display anything on it.
It doesn't appear that LCD2/VOUT2 is completely implemented yet. Is that correct?
Background:
Our hardware routes the appropriate VOUT2 signals directly from the AM572x processor to an SN65LVDS93 LVDS transmitter, and the LVDS output goes to our display connector along with an LCD enable signal (GPIO) and PWM backlight (ehrpwm1a).
The display turns on and rotates through color test images (primary colors and checkerboard). The colors look good. The backlight brightness is adjustable as expected.
My software is based on the recently released Linux SDK2.0.0.0 and the dts configuration for my display is below:
/ {
aliases {
display0 = &lcd0;
display1 = &hdmi0;
};
backlight: backlight {
status = "okay";
compatible = "pwm-backlight";
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
lcd0: display {
status = "okay";
compatible = "ETM0700G0DH6", "panel-dpi";
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins &display_en_pin>;
enable-gpios = <&gpio8 23 GPIO_ACTIVE_LOW>;
label = "lcd2";
panel-timing {
clock-frequency = <40000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <40>;
hback-porch = <216>;
hsync-len = <128>;
vback-porch = <35>;
vfront-porch = <10>;
vsync-len = <2>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <1>;
};
port {
lcd_in: endpoint {
remote-endpoint = <&dpi_out>;
};
};
};
};
&dss {
ports {
#address-cells = <1>;
#size-cells = <0>;
port {
reg = <1>;
dpi_out: endpoint {
remote-endpoint = <&lcd_in>;
data-lines = <24>;
};
};
};
};
Debug
I have modified drivers/video/fbdev/omap2/dss/dss.c:dss_dpi_select_source_dra7xx() to select the source appropriately for OMAP_DSS_CHANNEL_LCD2 in addition to OMAP_DSS_CHANNEL_LCD, and although it set DSS_CTRL to select LCD2 as the parallel output, it did not resolve any of the errors I am seeing. Also, the debugfs omapdss clk output is showing that there is no pclk or lclk set for LCD2, but I can't find anything in particular that explains why the PLL wouldn't be configured correctly. If I configure the lcd0 port to use reg = <0>, which corresponds to OMAP_DSS_CHANNEL_LCD and is not supported for VOUT2, the LCD1 channel has the proper 40Mhz pclk I am setting, LCD2 channel has the DSS_FCK, and I see no errors. But of course that does not output anything on VOUT2.
Furthermore, I am seeing
[ 2.421133] omapdrm omapdrm.0: lcd2: timeout waiting for enable
[ 2.471129] omapdrm omapdrm.0: atomic complete timeout (pipe 1)!
during boot, and am hitting a couple BUG_ON scenarios related to the DISPC_CONTROL2.GOWB register bit (as seen in attached the kernel_boot.log).
My results are the same with or without HDMI configured.
Any thoughts? I have been going over the registers and before I dive even deeper, I'm hoping for additional input.
Thanks,
Russell Robinson
# cat /sys/kernel/debug/omapdss/dss DSS_REVISION 00000061 DSS_SYSCONFIG 00000000 DSS_SYSSTATUS 00000001 DSS_CONTROL 00021000 # cat /sys/kernel/debug/omapdss/clk - DSS - DSS_FCK (DSS_CLK) = 192000000 - DISPC - dispc fclk source = DSS_FCK (DSS_CLK) fck 192000000 - DISPC-CORE-CLK - lck 192000000 lck div 1 - LCD - LCD clk source = DSS_FCK (DSS_CLK) lck 48000000 lck div 4 pck 48000000 pck div 1 - LCD2 - LCD2 clk source = DSI_PLL2_HSDIV_DISPC (DPLL_DSI1_C_CLK1) lck 0 lck div 1 pck 0 pck div 1 - LCD3 - LCD3 clk source = DSS_FCK (DSS_CLK) lck 48000000 lck div 4 pck 48000000 pck div 1 # cat /sys/kernel/debug/omapdss/dispc DISPC_REVISION 00000051 DISPC_SYSCONFIG 00002015 DISPC_SYSSTATUS 00000001 DISPC_IRQSTATUS 00000000 DISPC_IRQENABLE 0016964c DISPC_CONTROL 00018002 DISPC_CONFIG 00000004 DISPC_CAPABLE 00000000 DISPC_LINE_STATUS 00000000 DISPC_LINE_NUMBER 00000000 DISPC_GLOBAL_ALPHA ffffffff DISPC_CONTROL2 00000329 DISPC_CONFIG2 00000000 DISPC_CONTROL3 00000000 DISPC_CONFIG3 00000000 DISPC_GLOBAL_MFLAG_ATTRIBUTE 00000001 DISPC_DEFAULT_COLOR(LCD) 00000000 DISPC_TRANS_COLOR(LCD) 00000000 DISPC_SIZE_MGR(LCD) 00000000 DISPC_TIMING_H(LCD) 00000000 DISPC_TIMING_V(LCD) 00000000 DISPC_POL_FREQ(LCD) 00000000 DISPC_DIVISORo(LCD) 00040001 DISPC_DATA_CYCLE1(LCD) 00000000 DISPC_DATA_CYCLE2(LCD) 00000000 DISPC_DATA_CYCLE3(LCD) 00000000 DISPC_CPR_COEF_R(LCD) 00000000 DISPC_CPR_COEF_G(LCD) 00000000 DISPC_CPR_COEF_B(LCD) 00000000 DISPC_DEFAULT_COLOR(TV) 00000000 DISPC_TRANS_COLOR(TV) 00000000 DISPC_SIZE_MGR(TV) 0437077f DISPC_DEFAULT_COLOR(LCD2) 00000000 DISPC_TRANS_COLOR(LCD2) 00000000 DISPC_SIZE_MGR(LCD2) 01df031f DISPC_TIMING_H(LCD2) 0d70277f DISPC_TIMING_V(LCD2) 02300a01 DISPC_POL_FREQ(LCD2) 00030000 DISPC_DIVISORo(LCD2) 00010001 DISPC_DATA_CYCLE1(LCD2) 00000000 DISPC_DATA_CYCLE2(LCD2) 00000000 DISPC_DATA_CYCLE3(LCD2) 00000000 DISPC_CPR_COEF_R(LCD2) 00000000 DISPC_CPR_COEF_G(LCD2) 00000000 DISPC_CPR_COEF_B(LCD2) 00000000 DISPC_DEFAULT_COLOR(LCD3) 00000000 DISPC_TRANS_COLOR(LCD3) 00000000 DISPC_SIZE_MGR(LCD3) 00000000 DISPC_TIMING_H(LCD3) 00000000 DISPC_TIMING_V(LCD3) 00000000 DISPC_POL_FREQ(LCD3) 00000000 DISPC_DIVISORo(LCD3) 00040001 DISPC_DATA_CYCLE1(LCD3) 00000000 DISPC_DATA_CYCLE2(LCD3) 00000000 DISPC_DATA_CYCLE3(LCD3) 00000000 DISPC_CPR_COEF_R(LCD3) 00000000 DISPC_CPR_COEF_G(LCD3) 00000000 DISPC_CPR_COEF_B(LCD3) 00000000 DISPC_OVL_BA0(GFX) 7efa7000 DISPC_OVL_BA1(GFX) 7efa7000 DISPC_OVL_POSITION(GFX) 00000000 DISPC_OVL_SIZE(GFX) 0437077f DISPC_OVL_ATTRIBUTES(GFX) 02004191 DISPC_OVL_FIFO_THRESHOLD(GFX) 07ff07f8 DISPC_OVL_FIFO_SIZE_STATUS(GFX) 00000500 DISPC_OVL_ROW_INC(GFX) 00000001 DISPC_OVL_PIXEL_INC(GFX) 00000001 DISPC_OVL_PRELOAD(GFX) 000007ff DISPC_OVL_MFLAG_THRESHOLD(GFX) 05000400 DISPC_OVL_WINDOW_SKIP(GFX) 00000000 DISPC_OVL_TABLE_BA(GFX) 00000000 DISPC_OVL_BA0(VID1) 7ee30000 DISPC_OVL_BA1(VID1) 7ee30000 DISPC_OVL_POSITION(VID1) 00000000 DISPC_OVL_SIZE(VID1) 01df031f DISPC_OVL_ATTRIBUTES(VID1) 42a08011 DISPC_OVL_FIFO_THRESHOLD(VID1) 07ff07f8 DISPC_OVL_FIFO_SIZE_STATUS(VID1) 00000800 DISPC_OVL_ROW_INC(VID1) 00000001 DISPC_OVL_PIXEL_INC(VID1) 00000001 DISPC_OVL_PRELOAD(VID1) 000007ff DISPC_OVL_MFLAG_THRESHOLD(VID1) 05000400 DISPC_OVL_FIR(VID1) 04000400 DISPC_OVL_PICTURE_SIZE(VID1) 01df031f DISPC_OVL_ACCU0(VID1) 00000000 DISPC_OVL_ACCU1(VID1) 00000000 DISPC_OVL_BA0_UV(VID1) 00000000 DISPC_OVL_BA1_UV(VID1) 00000000 DISPC_OVL_FIR2(VID1) 04000400 DISPC_OVL_ACCU2_0(VID1) 00000000 DISPC_OVL_ACCU2_1(VID1) 00000000 DISPC_OVL_ATTRIBUTES2(VID1) 00000000 DISPC_OVL_BA0(VID2) 00000000 DISPC_OVL_BA1(VID2) 00000000 DISPC_OVL_POSITION(VID2) 00000000 DISPC_OVL_SIZE(VID2) 00000000 DISPC_OVL_ATTRIBUTES(VID2) 02808400 DISPC_OVL_FIFO_THRESHOLD(VID2) 07ff07f8 DISPC_OVL_FIFO_SIZE_STATUS(VID2) 00000800 DISPC_OVL_ROW_INC(VID2) 00000001 DISPC_OVL_PIXEL_INC(VID2) 00000001 DISPC_OVL_PRELOAD(VID2) 000007ff DISPC_OVL_MFLAG_THRESHOLD(VID2) 05000400 DISPC_OVL_FIR(VID2) 04000400 DISPC_OVL_PICTURE_SIZE(VID2) 00000000 DISPC_OVL_ACCU0(VID2) 00000000 DISPC_OVL_ACCU1(VID2) 00000000 DISPC_OVL_BA0_UV(VID2) 00000000 DISPC_OVL_BA1_UV(VID2) 00000000 DISPC_OVL_FIR2(VID2) 04000400 DISPC_OVL_ACCU2_0(VID2) 00000000 DISPC_OVL_ACCU2_1(VID2) 00000000 DISPC_OVL_ATTRIBUTES2(VID2) 00000000 DISPC_OVL_BA0(VID3) 00000000 DISPC_OVL_BA1(VID3) 00000000 DISPC_OVL_POSITION(VID3) 00000000 DISPC_OVL_SIZE(VID3) 00000000 DISPC_OVL_ATTRIBUTES(VID3) 02808400 DISPC_OVL_FIFO_THRESHOLD(VID3) 07ff07f8 DISPC_OVL_FIFO_SIZE_STATUS(VID3) 00000800 DISPC_OVL_ROW_INC(VID3) 00000001 DISPC_OVL_PIXEL_INC(VID3) 00000001 DISPC_OVL_PRELOAD(VID3) 000007ff DISPC_OVL_MFLAG_THRESHOLD(VID3) 05000400 DISPC_OVL_FIR(VID3) 04000400 DISPC_OVL_PICTURE_SIZE(VID3) 00000000 DISPC_OVL_ACCU0(VID3) 00000000 DISPC_OVL_ACCU1(VID3) 00000000 DISPC_OVL_BA0_UV(VID3) 00000000 DISPC_OVL_BA1_UV(VID3) 00000000 DISPC_OVL_FIR2(VID3) 04000400 DISPC_OVL_ACCU2_0(VID3) 00000000 DISPC_OVL_ACCU2_1(VID3) 00000000 DISPC_OVL_ATTRIBUTES2(VID3) 00000000 DISPC_OVL_FIR_COEF_H_0(VID1) 00800000 DISPC_OVL_FIR_COEF_H_1(VID1) 0e7df601 DISPC_OVL_FIR_COEF_H_2(VID1) 2172f102 DISPC_OVL_FIR_COEF_H_3(VID1) 3762f001 DISPC_OVL_FIR_COEF_H_4(VID1) f24e4ef2 DISPC_OVL_FIR_COEF_H_5(VID1) f06237f6 DISPC_OVL_FIR_COEF_H_6(VID1) f17221fa DISPC_OVL_FIR_COEF_H_7(VID1) f67d0efe DISPC_OVL_FIR_COEF_HV_0(VID1) 00800000 DISPC_OVL_FIR_COEF_HV_1(VID1) 0e7df6fe DISPC_OVL_FIR_COEF_HV_2(VID1) 2172f1fa DISPC_OVL_FIR_COEF_HV_3(VID1) 3762f0f6 DISPC_OVL_FIR_COEF_HV_4(VID1) f24e4e00 DISPC_OVL_FIR_COEF_HV_5(VID1) f0623701 DISPC_OVL_FIR_COEF_HV_6(VID1) f1722102 DISPC_OVL_FIR_COEF_HV_7(VID1) f67d0e01 DISPC_OVL_CONV_COEF_0(VID1) 0199012a DISPC_OVL_CONV_COEF_1(VID1) 012a0000 DISPC_OVL_CONV_COEF_2(VID1) 079c0730 DISPC_OVL_CONV_COEF_3(VID1) 0000012a DISPC_OVL_CONV_COEF_4(VID1) 00000205 DISPC_OVL_FIR_COEF_V_0(VID1) 00000000 DISPC_OVL_FIR_COEF_V_1(VID1) 0000fe01 DISPC_OVL_FIR_COEF_V_2(VID1) 0000fa02 DISPC_OVL_FIR_COEF_V_3(VID1) 0000f601 DISPC_OVL_FIR_COEF_V_4(VID1) 000000f2 DISPC_OVL_FIR_COEF_V_5(VID1) 000001f6 DISPC_OVL_FIR_COEF_V_6(VID1) 000002fa DISPC_OVL_FIR_COEF_V_7(VID1) 000001fe DISPC_OVL_FIR_COEF_H2_0(VID1) 00000000 DISPC_OVL_FIR_COEF_H2_1(VID1) 00000000 DISPC_OVL_FIR_COEF_H2_2(VID1) 00000000 DISPC_OVL_FIR_COEF_H2_3(VID1) 00000000 DISPC_OVL_FIR_COEF_H2_4(VID1) 00000000 DISPC_OVL_FIR_COEF_H2_5(VID1) 00000000 DISPC_OVL_FIR_COEF_H2_6(VID1) 00000000 DISPC_OVL_FIR_COEF_H2_7(VID1) 00000000 DISPC_OVL_FIR_COEF_HV2_0(VID1) 00000000 DISPC_OVL_FIR_COEF_HV2_1(VID1) 00000000 DISPC_OVL_FIR_COEF_HV2_2(VID1) 00000000 DISPC_OVL_FIR_COEF_HV2_3(VID1) 00000000 DISPC_OVL_FIR_COEF_HV2_4(VID1) 00000000 DISPC_OVL_FIR_COEF_HV2_5(VID1) 00000000 DISPC_OVL_FIR_COEF_HV2_6(VID1) 00000000 DISPC_OVL_FIR_COEF_HV2_7(VID1) 00000000 DISPC_OVL_FIR_COEF_V2_0(VID1) 00000000 DISPC_OVL_FIR_COEF_V2_1(VID1) 00000000 DISPC_OVL_FIR_COEF_V2_2(VID1) 00000000 DISPC_OVL_FIR_COEF_V2_3(VID1) 00000000 DISPC_OVL_FIR_COEF_V2_4(VID1) 00000000 DISPC_OVL_FIR_COEF_V2_5(VID1) 00000000 DISPC_OVL_FIR_COEF_V2_6(VID1) 00000000 DISPC_OVL_FIR_COEF_V2_7(VID1) 00000000 DISPC_OVL_FIR_COEF_H_0(VID2) 00000000 DISPC_OVL_FIR_COEF_H_1(VID2) 00000000 DISPC_OVL_FIR_COEF_H_2(VID2) 00000000 DISPC_OVL_FIR_COEF_H_3(VID2) 00000000 DISPC_OVL_FIR_COEF_H_4(VID2) 00000000 DISPC_OVL_FIR_COEF_H_5(VID2) 00000000 DISPC_OVL_FIR_COEF_H_6(VID2) 00000000 DISPC_OVL_FIR_COEF_H_7(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_0(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_1(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_2(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_3(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_4(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_5(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_6(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_7(VID2) 00000000 DISPC_OVL_CONV_COEF_0(VID2) 0199012a DISPC_OVL_CONV_COEF_1(VID2) 012a0000 DISPC_OVL_CONV_COEF_2(VID2) 079c0730 DISPC_OVL_CONV_COEF_3(VID2) 0000012a DISPC_OVL_CONV_COEF_4(VID2) 00000205 DISPC_OVL_FIR_COEF_V_0(VID2) 00000000 DISPC_OVL_FIR_COEF_V_1(VID2) 00000000 DISPC_OVL_FIR_COEF_V_2(VID2) 00000000 DISPC_OVL_FIR_COEF_V_3(VID2) 00000000 DISPC_OVL_FIR_COEF_V_4(VID2) 00000000 DISPC_OVL_FIR_COEF_V_5(VID2) 00000000 DISPC_OVL_FIR_COEF_V_6(VID2) 00000000 DISPC_OVL_FIR_COEF_V_7(VID2) 00000000 DISPC_OVL_FIR_COEF_H2_0(VID2) 00000000 DISPC_OVL_FIR_COEF_H2_1(VID2) 00000000 DISPC_OVL_FIR_COEF_H2_2(VID2) 00000000 DISPC_OVL_FIR_COEF_H2_3(VID2) 00000000 DISPC_OVL_FIR_COEF_H2_4(VID2) 00000000 DISPC_OVL_FIR_COEF_H2_5(VID2) 00000000 DISPC_OVL_FIR_COEF_H2_6(VID2) 00000000 DISPC_OVL_FIR_COEF_H2_7(VID2) 00000000 DISPC_OVL_FIR_COEF_HV2_0(VID2) 00000000 DISPC_OVL_FIR_COEF_HV2_1(VID2) 00000000 DISPC_OVL_FIR_COEF_HV2_2(VID2) 00000000 DISPC_OVL_FIR_COEF_HV2_3(VID2) 00000000 DISPC_OVL_FIR_COEF_HV2_4(VID2) 00000000 DISPC_OVL_FIR_COEF_HV2_5(VID2) 00000000 DISPC_OVL_FIR_COEF_HV2_6(VID2) 00000000 DISPC_OVL_FIR_COEF_HV2_7(VID2) 00000000 DISPC_OVL_FIR_COEF_V2_0(VID2) 00000000 DISPC_OVL_FIR_COEF_V2_1(VID2) 00000000 DISPC_OVL_FIR_COEF_V2_2(VID2) 00000000 DISPC_OVL_FIR_COEF_V2_3(VID2) 00000000 DISPC_OVL_FIR_COEF_V2_4(VID2) 00000000 DISPC_OVL_FIR_COEF_V2_5(VID2) 00000000 DISPC_OVL_FIR_COEF_V2_6(VID2) 00000000 DISPC_OVL_FIR_COEF_V2_7(VID2) 00000000 DISPC_OVL_FIR_COEF_H_0(VID3) 00000000 DISPC_OVL_FIR_COEF_H_1(VID3) 00000000 DISPC_OVL_FIR_COEF_H_2(VID3) 00000000 DISPC_OVL_FIR_COEF_H_3(VID3) 00000000 DISPC_OVL_FIR_COEF_H_4(VID3) 00000000 DISPC_OVL_FIR_COEF_H_5(VID3) 00000000 DISPC_OVL_FIR_COEF_H_6(VID3) 00000000 DISPC_OVL_FIR_COEF_H_7(VID3) 00000000 DISPC_OVL_FIR_COEF_HV_0(VID3) 00000000 DISPC_OVL_FIR_COEF_HV_1(VID3) 00000000 DISPC_OVL_FIR_COEF_HV_2(VID3) 00000000 DISPC_OVL_FIR_COEF_HV_3(VID3) 00000000 DISPC_OVL_FIR_COEF_HV_4(VID3) 00000000 DISPC_OVL_FIR_COEF_HV_5(VID3) 00000000 DISPC_OVL_FIR_COEF_HV_6(VID3) 00000000 DISPC_OVL_FIR_COEF_HV_7(VID3) 00000000 DISPC_OVL_CONV_COEF_0(VID3) 0199012a DISPC_OVL_CONV_COEF_1(VID3) 012a0000 DISPC_OVL_CONV_COEF_2(VID3) 079c0730 DISPC_OVL_CONV_COEF_3(VID3) 0000012a DISPC_OVL_CONV_COEF_4(VID3) 00000205 DISPC_OVL_FIR_COEF_V_0(VID3) 00000000 DISPC_OVL_FIR_COEF_V_1(VID3) 00000000 DISPC_OVL_FIR_COEF_V_2(VID3) 00000000 DISPC_OVL_FIR_COEF_V_3(VID3) 00000000 DISPC_OVL_FIR_COEF_V_4(VID3) 00000000 DISPC_OVL_FIR_COEF_V_5(VID3) 00000000 DISPC_OVL_FIR_COEF_V_6(VID3) 00000000 DISPC_OVL_FIR_COEF_V_7(VID3) 00000000 DISPC_OVL_FIR_COEF_H2_0(VID3) 00000000 DISPC_OVL_FIR_COEF_H2_1(VID3) 00000000 DISPC_OVL_FIR_COEF_H2_2(VID3) 00000000 DISPC_OVL_FIR_COEF_H2_3(VID3) 00000000 DISPC_OVL_FIR_COEF_H2_4(VID3) 00000000 DISPC_OVL_FIR_COEF_H2_5(VID3) 00000000 DISPC_OVL_FIR_COEF_H2_6(VID3) 00000000 DISPC_OVL_FIR_COEF_H2_7(VID3) 00000000 DISPC_OVL_FIR_COEF_HV2_0(VID3) 00000000 DISPC_OVL_FIR_COEF_HV2_1(VID3) 00000000 DISPC_OVL_FIR_COEF_HV2_2(VID3) 00000000 DISPC_OVL_FIR_COEF_HV2_3(VID3) 00000000 DISPC_OVL_FIR_COEF_HV2_4(VID3) 00000000 DISPC_OVL_FIR_COEF_HV2_5(VID3) 00000000 DISPC_OVL_FIR_COEF_HV2_6(VID3) 00000000 DISPC_OVL_FIR_COEF_HV2_7(VID3) 00000000 DISPC_OVL_FIR_COEF_V2_0(VID3) 00000000 DISPC_OVL_FIR_COEF_V2_1(VID3) 00000000 DISPC_OVL_FIR_COEF_V2_2(VID3) 00000000 DISPC_OVL_FIR_COEF_V2_3(VID3) 00000000 DISPC_OVL_FIR_COEF_V2_4(VID3) 00000000 DISPC_OVL_FIR_COEF_V2_5(VID3) 00000000 DISPC_OVL_FIR_COEF_V2_6(VID3) 00000000 DISPC_OVL_FIR_COEF_V2_7(VID3) 00000000
