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POSTDIV and PLLDIV3 for OMAPL137

zhangyg44396
Intellectual 400 points

Hi

Recently I am working with a project. I design  a 8x serial communication port board to use with OMAPL137 DSP board.

I used two ST16C554, each with 4 serial port, so total 8 serial port there.

The 8 bytes data bus from ST16C554 are connected to EMA_D[0] -- EMA_D[7] respectively.

These serial port base address are mapped to EMIFA base address.

Now I can send data and receive date through the serial port by continuely monitor the serial port register status.

Now the problem is I have to set POSTDIV to 0x00080009 or larger in order to make the expanded serial communication work well.

But the default value of POSTDIV is 0x00080001, and this value make the built-in uarts work well.

If POSTDIV is big than 0x00080003, the built-in uart could not work well.

I have read some article and I found the PLLDIV3 is for EMIFA, but it is no use to adjust PLLDIV3 alone.

It seems that only the POSTDIV play an important role in this.

Is it right that I do ? How should I do the next ?

I would be really grateful for your help

Please forgive my bad english.

Thanks

  • 0
    TI__Expert 8785 points

    If you are looking to slow down only the EMIFA clock, it is best to change PLLDIV3, rather than POSTDIV.  Changing POSTDIV will affect the operating speed of the entire device (DSP, ARM, UARTs, all peripherals, etc).  For more information on the device clocking, section 7 of the system guide (http://focus.ti.com/lit/ug/sprug84c/sprug84c.pdf) has a good reference block diagram.

    I noticed that you said that adjusting PLLDIV3 alone is no use.  Which article are you refering to?

    - Christina

  • 0 in reply to clam
    Intellectual 400 points

    Hi I understand little more on this.

    Changing PLLDIV3 under CCS environment does not take affect unless you restart CCS.

    while changing POSTDIV under CCS take affect immediately.

  • 0 in reply to zhangyg44396
    TI__Guru* 83935 points

    Hi

    zhangyg said:
    Changing PLLDIV3 under CCS environment does not take affect unless you restart CCS.

    Are you following the sequence provided in the system guide ? To change the SYSCLK divider values via PLLDIV you need to follow the sequence in Section 8.2.2.3 in the system guide, writing to the PLLDIVx.RATIO bits alone will not cause a frequency change.

    zhangyg said:
    while changing POSTDIV under CCS take affect immediately

    This is expected, modifying value of POSTDIV or PREDIV register (say via memory window in CCS) will immediately cause a frequency transition.

    Regards

    Mukul