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Why do we need to define different McBSP configuations for Control(McBSP0) and data(McBSP1) ?

hello All,

While coding in CCSv5.5 for audio applications where C6713 has to read audio data through line in pin.

Why do we need to provide different  Mcbsp configuration setting for Control and Data(We are also defining codec configuration for audio read).

McBSP0 should provide the codec with all the controls, why do we need different data configuration..?

My program goes like this

1. include files

2. MCBSP_Config mcbspCfgControl={................................}

3. MCBSP_Config mcbspCfgData={................................} 

4.codecConfig={..................................}

5. main program and other program functions. 

Thanks 

Nageshwar

  • Dear Nageshwar,
    What you are trying to do and requirement please ?
    Which example are you referring ?
    Are you using TI example code or your own code ?

    Can you please provide the package or example that you are using ?

    C:\ti\C6xCSL\examples\c6000\dsk6713\csl\mcbsp\mcbsp1
  • Nageshwar,

    As I mentioned in your other thread here, you will want to refer to the AIC23 datasheet for more detail on how that device operates and what its hardware requirements are for interfacing it to the C6713.

    Since you were reading through the C6x16 Integration Workshop for the other thread at Sivaraj's good suggestion, I will refer you to chapter 6 McBSP of that course. That section describes the McBSP operation in good detail (since it is a DSP workshop, of course) and it provides a slide showing the AIC23's logical hardware configuration as well as logical connections used on the DSK to connect between the C6713 and the AIC23.

    Nageshwar Singh said:

    Why do we need to provide different  Mcbsp configuration setting for Control and Data(We are also defining codec configuration for audio read).

    McBSP0 should provide the codec with all the controls, why do we need different data configuration..?

    All of the connections on the board and the software in the examples are used to meet the requirements of the AIC23 as stated in that datasheet. If you know a way to connect to the AIC23 without doing it as was done on the DSK, you are very clever. But the board uses the connections shown so the software for the DSK must use both McBSP ports. When you build your own custom board, you will be able to use your better method. Please post that method on the forum for others to use your method on their custom boards.

    But for the DSK, you have the examples to work with.

    Regards,
    RandyP

  • Thanks RandyP for your reply.

    My Question is retarding doubt on McbSp Coding for getting audio data (16 bit samples ) . Now for getting samples i have to Configure McbSp0 ,McbSp1 and AIC23 Codec.
    I am getting the data but its not continuous I am missing many samples.I think that is due to Clocking and framing. My codec is set to 48 khz frequency and and McBSP0 is configured to external clocking (slave), Frame with of 1 bit , and frame sync period of (48khz /16 as data has to 16 bits long ...)

    Here my code, I have used the code from mcbsp.c from "IW6000 Labs Folder" location C:\IW6000\labs\audioapp provided by Sivraj


    #include "csl.h"
    #include "dsk6713.h"
    #include "dsk6713_aic23.h"
    #include "stdlib.h"
    #include "math.h"
    #include "csl_mcbsp.h"



    MCBSP_Config mcbspCfgControl = {
    MCBSP_SPCR_RMK(
    MCBSP_SPCR_FREE_NO, /* Free-running mode is disabled. During emulation halt, SOFT bit determines operation of McBSP */
    MCBSP_SPCR_SOFT_NO, /* Soft mode is disabled. Serial port clock stops immediately during emulation halt, thus aborting any transmissions.*/
    MCBSP_SPCR_FRST_YES, /*Frame-sync generator reset bit. :: Frame-synchronization logic is reset. Frame-sync signal (FSG) is not generated by the sample-rate generator.*/
    MCBSP_SPCR_GRST_YES, /* Sample-rate generator reset bit.:: Sample-rate generator is reset.*/
    MCBSP_SPCR_XINTM_XRDY, /*Transmit interrupt (XINT) mode bit.:: XINT is driven by XRDY (end-of-word) and end-of-frame in A-bis mode.*/
    MCBSP_SPCR_XSYNCERR_NO, /* No synchronization error is detected.*/
    MCBSP_SPCR_XRST_YES, /*Transmitter reset bit resets or enables the transmitter. ::Serial port transmitter is disabled and in reset state. */
    MCBSP_SPCR_DLB_OFF, /* Digital loop back mode is disabled. */
    MCBSP_SPCR_RJUST_RZF, /* Receive sign-extension and justification mode bit.::Right-justify and zero-fill MSBs in DRR. */
    MCBSP_SPCR_CLKSTP_NODELAY, /* In SPI mode with data sampled on rising edge (CLKXP = 0): Clock starts with rising edge without delay.*/
    MCBSP_SPCR_DXENA_OFF, /* For C621x/C671x and C64x DSP: DX enabler bit.: DX enabler is off.*/
    MCBSP_SPCR_RINTM_RRDY,/* RINT is driven by RRDY (end-of-word) and end-of-frame in A-bi mode.*/
    MCBSP_SPCR_RSYNCERR_NO,/* No synchronization error is detected.*/
    MCBSP_SPCR_RRST_YES /* The serial port receiver is disabled and in reset state.*/
    ),
    MCBSP_RCR_DEFAULT,
    MCBSP_XCR_RMK(
    MCBSP_XCR_XPHASE_SINGLE,/* Single-phase frame */
    MCBSP_XCR_XFRLEN2_OF(0),/* Specifies the transmit frame length (number of words) in phase 2.*/
    MCBSP_XCR_XWDLEN2_8BIT,/* Specifies the receive word length (number of bits) in phase 2: */
    MCBSP_XCR_XCOMPAND_MSB,/* Transmit companding mode bit, Modes other than 00 are only enabled when XWDLEN1/2 bit is 000 (indicating 8-bit data).&&&& No companding, data transfer starts with MSB first*/
    MCBSP_XCR_XFIG_NO, /* Transmit frame ignore bit.:: Transmit frame-synchronization pulses after the first pulse restarts the transfer.*/
    MCBSP_XCR_XDATDLY_0BIT, /* Transmit data delay bit. :: 0-bit data delay*/
    MCBSP_XCR_XFRLEN1_OF(0),/* Specifies the transmit frame length (number of words) in phase 1.*/
    MCBSP_XCR_XWDLEN1_16BIT,/* Specifies the receive word length (number of bits) in phase 1:*/
    MCBSP_XCR_XWDREVRS_DISABLE/* For C621x/C671x and C64x DSP: Transmit 32-bit bit reversal feature enable bit. :: 32-bit bit reversal is disabled.*/
    ),
    MCBSP_SRGR_RMK(
    MCBSP_SRGR_GSYNC_FREE,/* Sample-rate generator clock synchronization bit only used when the external clock (CLKS) drives the sample-rate generator clock (CLKSM = 0) :: The sample-rate generator clock (CLKG) is free running.*/
    MCBSP_SRGR_CLKSP_RISING,/* CLKS polarity clock edge select bit only used when the external clock (CLKS) drives the sample-rate generator clock (CLKSM = 0). :: Rising edge of CLKS generates CLKG and FSG*/
    MCBSP_SRGR_CLKSM_INTERNAL,/* MCBSP sample-rate generator clock mode bit. :: Sample-rate generator clock derived from CPU clock.*/
    MCBSP_SRGR_FSGM_DXR2XSR,/* Sample-rate generator transmit frame-synchronization mode bit used when FSXM = 1 in PCR :: Transmit frame-sync signal (FSX) due to DXR-to-XSR copy. ::When FSGM = 0, FWID bit and FPER bit are ignored.*/
    MCBSP_SRGR_FPER_OF(16),/* The value plus 1 specifies when the next frame-sync signal becomes active. Range: 1 to 4096 sample-rate generator clock (CLKG) periods.*/
    MCBSP_SRGR_FWID_OF(0),/* The value plus 1 specifies the width of the frame-sync pulse (FSG) during its active period.*/
    MCBSP_SRGR_CLKGDV_OF(0)/* The value is used as the divide-down number to generate the required sample-rate generator clock frequency.*/
    ),
    MCBSP_MCR_DEFAULT,

    MCBSP_PCR_RMK(
    MCBSP_PCR_XIOEN_SP, /* Transmit general-purpose I/O mode only when transmitter is disabled (XRST = 0 in SPCR). :: DX, FSX, and CLKX pins are configured as serial port pins and do not function as general-purpose I/O pins.*/
    MCBSP_PCR_RIOEN_SP, /* Receive general-purpose I/O mode only when receiver is disabled (RRST = 0 in SPCR). :: DR, FSR, CLKR, and CLKS pins are configured as serial port pins and do not function as general-purpose I/O pins.*/
    MCBSP_PCR_FSXM_INTERNAL, /* Transmit frame-synchronization mode bit. :: Frame-synchronization signal is determined by FSGM bit in SRGR.*/
    MCBSP_PCR_FSRM_EXTERNAL, /* Receive frame-synchronization mode bit. :: Frame-synchronization signal is derived from an external source. FSR is an input pin.*/
    MCBSP_PCR_CLKXM_OUTPUT, /* Transmitter clock mode bit. :: CLKX is an output pin and is driven by the internal sample-rate generator.*/
    MCBSP_PCR_CLKRM_INPUT, /* Receiver clock mode bit :: CLKR is an input pin and is driven by an external clock.*/
    MCBSP_PCR_CLKSSTAT_DEFAULT, /* CLKS pin status reflects value on CLKS pin when configured as a general-purpose input pin.*/
    MCBSP_PCR_DXSTAT_DEFAULT, /* DX pin status reflects value driven to DX pin when configured as a general-purpose output pin.*/
    MCBSP_PCR_FSXP_ACTIVELOW, /* Transmit frame-synchronization polarity bit. :: Transmit frame-synchronization pulse is active low.*/
    MCBSP_PCR_FSRP_DEFAULT, /* Receive frame-synchronization polarity bit. */
    MCBSP_PCR_CLKXP_FALLING, /* Transmit clock polarity bit. ::Transmit data sampled on falling edge of CLKX.*/
    MCBSP_PCR_CLKRP_DEFAULT /* Receive clock polarity bit. */
    )
    };

    MCBSP_Config mcbspCfgData = {
    MCBSP_SPCR_RMK(
    MCBSP_SPCR_FREE_NO, /* Free-running mode is disabled. During emulation halt, SOFT bit determines operation of McBSP.*/
    MCBSP_SPCR_SOFT_NO, /* Soft mode is disabled. Serial port clock stops immediately during emulation halt, thus aborting any transmissions.*/
    MCBSP_SPCR_FRST_YES, /* Frame-sync generator reset bit. :: Frame-synchronization logic is reset. Frame-sync signal (FSG) is not generated by the sample-rate generator.*/
    MCBSP_SPCR_GRST_YES, /* Sample-rate generator reset bit.:: Sample-rate generator is reset.*/
    MCBSP_SPCR_XINTM_XRDY, /* XINT is driven by XRDY (end-of-word) and end-of-frame in A-bis mode.*/
    MCBSP_SPCR_XSYNCERR_NO, /* No synchronization error is detected.*/
    MCBSP_SPCR_XRST_YES, /* Serial port transmitter is enabled. */
    MCBSP_SPCR_DLB_OFF, /* Digital loop back mode is disabled. */
    MCBSP_SPCR_RJUST_RZF, /* Right-justify and zero-fill MSBs in DRR.*/
    MCBSP_SPCR_CLKSTP_DISABLE, /* Clock stop mode is disabled. Normal clocking for non-SPI mode.*/
    MCBSP_SPCR_DXENA_OFF, /* For C621x/C671x and C64x DSP: DX enabler bit.: DX enabler is off.*/
    MCBSP_SPCR_RINTM_RRDY, /* RINT is driven by RRDY (end-of-word) and end-of-frame in A-bi mode.*/
    MCBSP_SPCR_RSYNCERR_NO, /* No synchronization error is detected.*/
    MCBSP_SPCR_RRST_YES /* The serial port receiver is disabled and in reset state.*/
    ),
    MCBSP_RCR_RMK(
    MCBSP_RCR_RPHASE_SINGLE, /* Single-phase frame*/
    MCBSP_RCR_RFRLEN2_DEFAULT,/*Specifies the transmit frame length (number of words) in phase 2 */
    MCBSP_RCR_RWDLEN2_DEFAULT,/* Specifies the receive word length (number of bits) in phase 2*/
    MCBSP_RCR_RCOMPAND_MSB,/*Transmit companding mode bit, Modes other than 00 are only enabled when XWDLEN1/2 bit is 000 (indicating 8-bit data) */
    MCBSP_RCR_RFIG_NO,/* Transmit frame ignore bit.:: Transmit frame-synchronization pulses after the first pulse restarts the transfer. */
    MCBSP_RCR_RDATDLY_0BIT,/*Transmit data delay bit. :: 0-bit data delay*/
    MCBSP_RCR_RFRLEN1_OF(0),/*Specifies the transmit frame length (number of words) in phase 1.*/
    MCBSP_RCR_RWDLEN1_16BIT,/*Specifies the receive word length (number of bits) in phase 1.Receive word length is 12 bits. */
    MCBSP_RCR_RWDREVRS_DISABLE/*32-bit bit reversal is disabled.*/
    ),
    MCBSP_XCR_RMK(
    MCBSP_XCR_XPHASE_SINGLE,/*Single-phase frame */
    MCBSP_XCR_XFRLEN2_DEFAULT,/* */
    MCBSP_XCR_XWDLEN2_DEFAULT,/**/
    MCBSP_XCR_XCOMPAND_MSB,/*Transmit companding mode bit, Modes other than 00 are only enabled when XWDLEN1/2 bit is 000 (indicating 8-bit data).&&&& No companding, data transfer starts with MSB first*/
    MCBSP_XCR_XFIG_NO,/* Transmit frame ignore bit.:: Transmit frame-synchronization pulses after the first pulse restarts the transfer.*/
    MCBSP_XCR_XDATDLY_0BIT,/*Transmit data delay bit. :: 0-bit data delay*/
    MCBSP_XCR_XFRLEN1_OF(0),/*Specifies the transmit frame length (number of words) in phase 1.*/
    MCBSP_XCR_XWDLEN1_16BIT,/**/
    MCBSP_XCR_XWDREVRS_DISABLE/** For C621x/C671x and C64x DSP: Transmit 32-bit bit reversal feature enable bit. :: 32-bit bit reversal is disabled*/
    ),
    MCBSP_SRGR_RMK(
    MCBSP_SRGR_GSYNC_FREE,/* Sample-rate generator clock synchronization bit only used when the external clock (CLKS) drives the sample-rate generator clock (CLKSM = 0) :: The sample-rate generator clock (CLKG) is free running.*/
    MCBSP_SRGR_CLKSP_RISING,/* CLKS polarity clock edge select bit only used when the external clock (CLKS) drives the sample-rate generator clock (CLKSM = 0). :: Rising edge of CLKS generates CLKG and FSG*/
    MCBSP_SRGR_CLKSM_INTERNAL,/* MCBSP sample-rate generator clock mode bit. :: Sample-rate generator clock derived from CPU clock.*/
    MCBSP_SRGR_FSGM_DXR2XSR,/* Sample-rate generator transmit frame-synchronization mode bit used when FSXM = 1 in PCR :: Transmit frame-sync signal (FSX) due to DXR-to-XSR copy. ::When FSGM = 0, FWID bit and FPER bit are ignored.*/
    MCBSP_SRGR_FPER_OF(16),/* The value plus 1 specifies when the next frame-sync signal becomes active. Range: 1 to 4096 sample-rate generator clock (CLKG) periods.*/
    MCBSP_SRGR_FWID_OF(0),/* The value plus 1 specifies the width of the frame-sync pulse (FSG) during its active period.*/
    MCBSP_SRGR_CLKGDV_OF(0)/* The value is used as the divide-down number to generate the required sample-rate generator clock frequency.*/
    ),
    // MCBSP_SRGR_DEFAULT,
    MCBSP_MCR_DEFAULT,
    //C67x Needs RCER
    //MCBSP_RCER_DEFAULT, // C67x ONLY, C67x ONLY

    //C64x Needs RCER0-3
    //MCBSP_RCERE0_DEFAULT, // C64x ONLY, C64x ONLY
    //MCBSP_RCERE1_DEFAULT, // C64x ONLY, C64x ONLY
    //MCBSP_RCERE2_DEFAULT, // C64x ONLY, C64x ONLY
    //MCBSP_RCERE3_DEFAULT, // C64x ONLY, C64x ONLY

    //C67x Needs XCER
    //MCBSP_XCER_DEFAULT, // C67x ONLY, C67x ONLY

    //C64x Needs RCER0-3
    //MCBSP_XCERE0_DEFAULT, // C64x ONLY, C64x ONLY
    //MCBSP_XCERE1_DEFAULT, // C64x ONLY, C64x ONLY
    //MCBSP_XCERE2_DEFAULT, // C64x ONLY, C64x ONLY
    //MCBSP_XCERE3_DEFAULT, // C64x ONLY, C64x ONLY
    MCBSP_PCR_RMK(
    MCBSP_PCR_XIOEN_SP,/*Transmit general-purpose I/O mode only when transmitter is disabled (XRST = 0 in SPCR). :: DX, FSX, and CLKX pins are configured as serial port pins and do not function as general-purpose I/O pins.*/
    MCBSP_PCR_RIOEN_SP,/*Receive general-purpose I/O mode only when receiver is disabled (RRST = 0 in SPCR). :: DR, FSR, CLKR, and CLKS pins are configured as serial port pins and do not function as general-purpose I/O pins.*/
    MCBSP_PCR_FSXM_EXTERNAL,/*Transmit frame-synchronization mode bit. :: Frame-synchronization signal is derived from an external source.*/
    MCBSP_PCR_FSRM_EXTERNAL,/* Receive frame-synchronization mode bit. :: Frame-synchronization signal is derived from an external source. FSR is an input pin.*/
    MCBSP_PCR_CLKXM_INPUT,/*Transmitter clock mode bit. ::CLKX is an input pin and is driven by an external clock.*/
    MCBSP_PCR_CLKRM_INPUT,/* Receiver clock mode bit :: CLKR is an input pin and is driven by an external clock.*/
    MCBSP_PCR_CLKSSTAT_DEFAULT,/* CLKS pin status reflects value on CLKS pin when configured as a general-purpose input pin.*/
    MCBSP_PCR_DXSTAT_DEFAULT,/* CLKS pin status reflects value on CLKS pin when configured as a general-purpose input pin.*/
    MCBSP_PCR_FSXP_ACTIVEHIGH,/* Transmit frame-synchronization polarity bit. :: Transmit frame-synchronization pulse is active high.*/
    MCBSP_PCR_FSRP_ACTIVEHIGH,/*Receive frame-synchronization polarity bit. ::Receive frame-synchronization pulse is active high..*/
    MCBSP_PCR_CLKXP_FALLING,/* Transmit clock polarity bit.:: Transmit data sampled on falling edge of CLKX.*/
    MCBSP_PCR_CLKRP_RISING/* Receive clock polarity bit. :: Receive data sampled on rising edge of CLKR.*/
    )
    };


    /* McBSP Handles */
    MCBSP_Handle hMcbsp0; // McBSP control handle
    MCBSP_Handle hMcbsp1; // McBSP data handle



    /*MCBSP_Config mcbspCfgControl = {
    0x00001000, // Serial Port Control Reg. (SPCR)
    0x00000040, // Receiver Control Reg. (RCR)
    0x00000040, // Transmitter Control Reg. (XCR)
    0x20001363, // Sample-Rate Generator Reg. (SRGR)
    0x00000000, // Multichannel Control Reg. (MCR)
    0x00000000, // Receiver Channel Enable (RCER)
    0x00000000, // Transmitter Channel Enable (XCER)
    0x00000A0A // Pin Control Reg. (PCR)
    };*/



    void initCodec(MCBSP_Handle hMcbsp0)
    {
    int i;
    short codecConfig[10] = {
    0x0017, // 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume
    0x0017, // 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume
    0x01f9, // 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume
    0x01f9, //3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume
    0x0011, // 4 DSK6713_AIC23_ANAPATH Analog audio path control
    0x0000, //5 DSK6713_AIC23_DIGPATH Digital audio path control
    0x0000, //6 DSK6713_AIC23_POWERDOWN Power down control
    0x0043, //7 DSK6713_AIC23_DIGIF Digital audio interface format
    0x0001, //8 DSK6713_AIC23_SAMPLERATE Sample rate control
    0x0001 //9 DSK6713_AIC23_DIGACT Digital interface activation


    };

    for (i = 0; i < 10; i++)
    {
    MCBSP_write(hMcbsp0,codecConfig[i]);

    MCBSP_write(hMcbsp0,(i << 9)|codecConfig[i]);
    }
    }

    /*
    void initMcBSP()
    { hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET);
    MCBSP_config(hMcbsp0, &mcbspCfgControl );
    initCodec(hMcbsp0);
    MCBSP_start (hMcbsp0, MCBSP_XMIT_START |
    MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 100);
    }
    */

    int initMcBSP()
    {
    /* Open McBSP for codec control */
    hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET);
    if (hMcbsp0 == INV)
    return FALSE;

    /* Open McBSP for codec data */
    hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
    if (hMcbsp1 == INV)
    return FALSE;

    /* Configure McBSP for control */
    MCBSP_config(hMcbsp0, &mcbspCfgControl);

    /* Configure McBSP for data */
    MCBSP_config(hMcbsp1, &mcbspCfgData); // still need to be figured out


    /* Call the provided codec initialiation routine */
    initCodec(hMcbsp0);

    /* Start McBSP for the codec control channel */
    MCBSP_start(hMcbsp0, MCBSP_XMIT_START |MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 220);



    /* Clear any garbage from the codec data port */
    if (MCBSP_rrdy(hMcbsp1))
    MCBSP_read(hMcbsp1);

    /* Start McBSP for the codec data channel */
    MCBSP_start(hMcbsp1, MCBSP_XMIT_START | MCBSP_RCV_START |MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 220);
    return TRUE;
    }




    /*
    DSK6713_AIC23_Config config = {
    0x0017,// 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume
    0x0017,// 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume
    0x01f9,// 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume
    0x01f9,// 3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume
    0x0011,// 4 DSK6713_AIC23_ANAPATH Analog audio path control
    0x0000,// 5 DSK6713_AIC23_DIGPATH Digital audio path control
    0x0000,// 6 DSK6713_AIC23_POWERDOWN Power down control
    0x0043,// 7 DSK6713_AIC23_DIGIF Digital audio interface format
    0x0001,// 8 DSK6713_AIC23_SAMPLERATE Sample rate control
    0x0001 // 9 DSK6713_AIC23_DIGACT Digital interface activation
    };
    */
    void main()
    {

    Uint32 stereo, *val;
    int dataPresent = 0,data,i=1;
    // Initialize BSL
    DSK6713_init();

    initMcBSP();
    while (1)
    {
    /* If McBSP doesn't have new data available, return false */
    if (!MCBSP_rrdy(hMcbsp1))
    {
    dataPresent=0;
    }
    else
    {
    dataPresent=1;
    }

    i=i+1; // for checking when do i get the data.
    /* Read the data */
    *val = MCBSP_read(hMcbsp1);
    data = *val;
    }
    }

    I this code i am not getting data on every loop instant.

    thanks
    Nageshwar
  • Nageshwar,

    Have we answered your original question about the two McBSP ports being needed? If so, please mark the answer post with Verify Answer so future users can search for that question and find that answer. When you start a new question, it is best to begin a new thread.

    In one of your threads here, I suggested you find the training workshop material to learn how to use the C6713 and to develop exactly what you are trying to do separately. Please go through that material and use the labs from that class exactly as they are and see if you can get them to work. As I recall, those labs build up to a working stereo input and stereo output audio application. If your cannot get that code to work exactly as it comes from the workshop, that is one issue to be addressed. If you make changes that do not work, then you have something to go back to and find what you have done wrong.

    Nageshwar Singh said:
    McBSP0 is configured to external clocking (slave), Frame with of 1 bit , and frame sync period of (48khz /16 as data has to 16 bits long ...)

    If you are receiving stereo data that is 16 bits for each of left and right, then the frame sync period would need to be 48kHz/32, although I think it is the inverse of that expression.

    Nageshwar Singh said:
    I this code i am not getting data on every loop instant.

    The workshop teaches you the things that need to be done to avoid losing samples or getting corrupted data. To tell you everything you might be doing wrong, I would be teaching that whole class. So you have that on TI.com. I am not in a position to debug 300 lines of code. But I can send you to the tested labs in the workshop.

    Regards,
    RandyP