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UART interrupt service routine for C674x DSP

Michael Greenspan
Intellectual 575 points

I have read through the material on the UART in the Technical Reference, and find it unclear exactly how to put together a "bullet proof" interrupt service routine...there does not seem to be any clear guidance on this issue.  I will be using the FIFO but not the EDMA.

When the interrupt occurs, it could be from FIFO reaching receive trigger level, or THRE, or receiver line status errors (OE, PE, FE, BI).  I would think the first thing to do is to read the IIR register to see what caused the interrupt (but sometimes more than one cause will be active, or another may occur while the interrupt service routine is executing).  Suppose there is a parity error and also THRE condition.  When I read the IIR, it also clears the THRE interrupt.   But since the line error has higher priority, that is what I will see in the INTID.   How will I ever know that the THRE condition also exists?  Maybe it is still set in the LSR?

Also...when should I clear the flag in the event manager?  After all the interrupting sources have been handled from the device?  I want to be sure there is no risk that an interrupt will be missed because of an event occurring at the wrong time in my sequence of instructions.

I know there are some examples in the starterware code and the PSP code, but they are not helpful in answering these questions.  For some of the other peripherals there were clear descriptions of what needed to be in the interrupt service routine and I would much appreciate the same for the UART

Thanks

  • 0
    Mastermind 6115 points

    but sometimes more than one cause will be active, or another may occur while the interrupt service routine is executing

    When you will be in interrupt service routine, that corresponding interrupt need to be disabled till the time routine doesn't finish.
    So their might not be possible the loss of Tx/Rx interrupt in this scenario.

    Tx interrupt might miss if both Tx interrupt and Rx interrupt occurs simultaneously as Rx is having higher priority then Tx ,
    but that scenario can be controlled in your application by having some locking mechanism over read and write functions of receiver and transmitter.
  • 0 in reply to Arvind Singh
    Intellectual 575 points

    I'm sorry, I cannot make any sense out of this answer.

    In the first part, are you saying that I should be clearing the bits in the IER register during the interrupt routine and then setting them at the end?    In the second part, you seem to be saying that there is a technical problem in the UART which is so severe that I cannot use in in full duplex operation?

    For the moment, the best solution I can come up with is this (operating in FIFO mode):

    1) Loop until the IIR IPEND bit goes to 1

    2) Within the loop,  if INTID is 2 or 4, read from the RBR until the LSR DR bit is clear

    3) If IER has transmit interrupts enabled, and there is data waiting to be sent, I write until there is no more to be sent or the transmit FIFO is full (16 bytes).  If no more to be sent, I disable transmit interrupts in the IER

    4) After this is all done, clear the flag for the UART in the event manager

    This seems to work OK.  My only concern is that these 16550 chips in their various incarnations/versions/implementations have had a history of subtle bugs and differences depending on manufacturer or part number suffix, and I wondered if there was a clearly defined recommendation that has been well tested for this particular version...kind of a detailed flow chart or sequence of operations that is sure not to cause problems.

    Thanks