Hello,
I am reading the DM365 VPFE datasheet spufg8b.pdf and I meet some problems understanding the text and diagram notes.
On page 344, 6.4.13, GCK_SDR.
The bit 0 CORE = RSZ Core Clock Enable described as follows :
When this bit is off, Resizer core (interpolator) is automatically bypassed (resizer-bypass mode of pass-through mode depending on SRC_FMT0 value).
In resizer-bypass mode or pass-through mode, no up-scaling or down scaling process is operated.
Rescaling : GCK_SDR=1, SRC_FMT0[BYPASSS]=0
Resizer bypass : GCK_SDR=0, SRC_FMT0[BYPASSS]=0
Pass-through : GCK_SDR=0, SRC_FMT0[BYPASSS]=1
with 0 off 1 on
We also find this description in the diagram in page 73 paragraph 4.7 IMAGING PIPE
What is strange si that for the mode rescaling we put : 1 in SRC_FMT0 and 0 in GCK_SDR meaning this last bit GCK_SDR must be set to 0 for rescaling. However 0 means off meaning the resizer is not working. So my question :
Is there an error in the bit definitions on the rescaling case on the table and on the diagram or did i miss something ?
Thanks for your help
