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[OMAPL137] debugging my board through armubl

Other Parts Discussed in Thread: OMAP-L137, 4428

I'm using the OMAP-L137. I've been working on a project for it for about 1.5 years. The boot process has not caused any problems until I got the new boards. I am trying to boot from SPI flash, and the Winbond parts work, but the Numonyx parts flash, but won't boot. These are the same Numonyx parts that worked on the previous rev of the board. I'm trying to figure out what is different. I'm pretty sure it is a HW change that is causing the problem. Here is what I have so far:

The DSP boots.

Armubl starts. I've captured the SPI traffic on a scope and I see the chip select bracketing a command to read followed by 7 reads. The first 3 seem to be the address width check, suggesting that the code things the address width is 24 bits. (This is correct for the part.) I do not see the chip select deassert/assert, but I see an addition 4 reads. I can't match that up to the code I see in armubl.

I would like to trace the activity from the width check to whereever the code goes next, because I think this may tell me something useful about the failure mode. It is unclear to me how to do this. (I'm willing to do the tracing in assembly, but I'm not sure how to connect to the ARM before it runs past the point.)

On the DSP side, I put a "while (pleaseWait)" at the beginning of the code and, after connecting, I change the value of pleaseWait from TRUE to FALSE. I would like to do something similar on the ARM side, but I have no symbol table info. Still, I'm guessing it can be done.

Remember, u-boot is not yet running, so the memory map is pretty much controlled by armubl and the gel file. Has anyone does this before?

  • Hi Flamingo,

    Have you changed anything in the new revision of the board?

    Because if the earlier board works for the same combination of armubl and gel file, then shouldnt it work with the same  code for the new board?

    Maybe ,then the problem exists at the hardware side.

    Something like the chip select of FLASH does not go low actually for the time when it should be reading data from flash.

    Have you tried probing the signals on CRO?

    Regards,

    Sid

  • Flamingo,

    Can you verify that the devices on the new boards have the same ROM code revision as your previous batch of boards?

    It should be possible to insert similar pleaseWait loops in the ARM UBL by polling a specific address location (with a pointer) that you can poke through CCS.

    -Tommy

  • I'm not sure how to check the ROM code version, but I know that the rev of OMAP is different. We had early release chips with SPI problems, etc. The current board uses revision 2 of the silicon.

    I'm not sure I was clear about the issue: the old version of the board boots with both Winbond and Numonyx parts. The new version boots with Winbond, but not Numonyx.

    I'm able to use the dsp spi flash writer project to flash all of the parts and I perform a full verify (wrote my own). The dspais, armubl, uboot, and kernel are the same on both flash brands.

    I'm still investigating...

  • It sounds like the L137 and SPI flash are ok since you can program and read-verify from them.  The ROM image has been updated between Rev 1.x and Rev2.0, but the SPI boot mode should be backward compatible.  In case you run out of debug options, can you try the new AISGen revision? http://focus.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=sprab04d

    -Tommy

  • (This post references file on my profile page.)

    I was mistaken when I said that dspais worked and armubl didn't. Instead, I've discovered that dspais is not running either. I've continued diagnosing, and I'm not sure that I've identified the problem, but I've found something curious. I'm hoping someone at TI can tell me if this might be my problem.

     

    I captured SPI traffic from the ROM boot for the OMAP-L137. I have no source code, but it was performing a (slow) read of flash starting at location 0, so I modified my version of the dsp-spi-flash-writer to perform its verify using a slow read (0x3 instead of the fast read 0xb). I then captured the dsp-spi-flash-writer traffic on the scope to see how it differs from the traffic during ROM boot. (I thought it might be an SCLK problem, since the Numonyx part is slower than the Winbond part.)

     

    In the file "tek00002.tif" you see the dsp-spi-flash-writer's version of a slow read from location 0. At the top of the display, you see the full buffer. The bottom is the zoomed section within the gray brackets. The magenta trace is the chip select. The green trace is the SIMO (M=OMAP). The cyan trace is the SOMI (S=Numonyx M25P128). The yellow trace is SCLK. At the bottom of the display, note that the SCLK frequency is 622.4kHz. (approximately matching my planned SCLK).

     

    In the file "tek00003.tif", you see the ROM boot's version of the same thing. The first thing you'll notice is that the SCLKs are not differentiatable at this zoom factor. That is, the SCLK in the ROM boot is much faster. In reality, it is about 10MHz. (within spec for the chip) You may also notice that there are several groups of SPI traffic. The first 3 groups each have 8 bytes and they are slow reads of 4 bytes each at 0, 4, and 8. The two groups of 4 have no new SIMO command, so are continued reads.

     

    In the file "tek00004.tif", you see a closeup of the last group of 4 and the last group of (very fast) 8 SCLKs.

    Finally, in file "tek00005.tif", I zoom into one of the fast SCLK groups. In this shot, the SCLK is about 77 MHz. This is beyond the tolerance of the

    Numonyx part. The command appears to be a slow read again (0x3). The Numonyx part is responding, but the SCLK does not meet the spec for the part. There is no more SPI traffic on the trace.

     

    I'm not sure what the logic is within the ROM boot program. I don't know why it is changing the SCLK speed. I don't know if additional SPI traffic appears at a much later time (after the scope's buffer).

     

    Please let me know if this is just an artifact of some logic that I'm unaware of or if this is an indication of a problem. (In the meantime, we're trying to order more Winbond parts.)

     

  • Flamingo,

    Can you repost the pictures?  I do not see any.

    How fast is the DSP running when you measure the SCLK?  I'm surprised that you are measuring 77MHz.

    -Tommy

  • The files are on the "Files" tab on my profile page. Their names are referenced in the text of my post. (Don't bother with other files that you see.)

  • Sorry, I didn't see the second question in your post. The majority of the circuitry on our board matches the EVM board that we got over a year ago. I don't have the circuit diagram near me, but I'm guessing that the OMAP has a 300 MHz clock. Did you find the photos from the scope measurements?

  • Flamingo,

    Can you verify the bootmode with the SYSCFG_BOOTCFG register?  SPI should not be running that fast during hardware ROM boot.  Can you try to flash a while(1) / NOP type of program into SPI and boot into that?

    -Tommy

  • When I set the switches in the position that I believe should boot from SPI flash, BOOTCFG = 0xe37d. When I set them in the position that I believe should allow me to run spi-flash-writer, BOOTCFG = 0xe3ff. I'm flipping two switches, so that makes sense.

    These same settings "work" (SPI Flash boot succeeds) on a board that has the Winbond part.

    spi-flash-writer works on both Numonyx and Winbond boards. I've modified spi-flash-writer to perform a full verify when I write each component to the Flash chip. All verifies pass. (Although my clock is much slower than I'm seeing during SPI Flash boot.)

  • If I understand your problem description, it seems to be the SPI0 peripheral frequency that is breaking the boot process.  What I can't figure out is how the SPI is operating at such a high frequency.  If we can use a dummy boot program that does not configure the PLL or any other functions, I would expect the SPI to stay at a reasonably slow frequency.  If that is the case, then it will be a process of finding out what part of the setup is configuring the SPI module to 77MHz.

    -Tommy

  • First a recap, and then some questions.

    I can successfully run the spi-flash-writer when the switch settings are set for that. I do use a GEL file when I connect for spi-flash-writer. I presume that the ROM bootloader does not try SPI accesses in this case. Therefore, the SPI setup is based on what occurs in the spi-flash-writer code (and the GEL file). Slow reads, fast reads, and writes all work.

    I can not successfully boot when I have the switches set for SPI flash boot. I presume that the ROM bootloader does perform the SPI setup in this case. It successfully performs 32 SPI accesses with an SCLK that is at an acceptable frequency. The 33rd SPI access is attempted with a SCLK frequency that is too high. If you look at the top of the tek00005.tif file, you see the entire capture buffer in miniature. The SCLK is the yellow trace. You see one "spike" on the trace followed by 32 accesses that "work" and 8 accesses that probably don't. No other SPI accesses appear within the captured buffer. The lower part of tek00005.tif is a closeup of one of the fast accesses.

    Note that the SPI captures are the first accesses triggered after a boot. If I connect after the failure, the program counter is still in the 0x007xxxxx memory space (at the IDLE statement). I believe this means that it never executes the DSPAIS code, which is at 0x80010000. If I reset after connecting, I can step through the ROM bootloader and it ends up at the same program counter setting. In the instance of stepping through the sequence, I do not necessarily expect the boot to succeed because there are probably timing loops in the ROM bootloader that may not survive the stepping process.

    I have no source code for the ROM boot, but somewhere between the 32nd and 33rd SPI access, something bad has happened. Each of the first sets of 8 are 4-byte reads at SPI addresses 0, 4, and 8. In each instance, the read command is issued (4 of the bytes) and 4 bytes are read (the other 4 bytes of the 8 byte sequence). That is, there are 3 slow read commands. The next two groups of 4 are continued reads (from the read at address 8. That means that they are reads of 4 bytes each for address 0xc and 0x10. The ROM bootloader has successfully read 0x14 bytes from the SPI flash. The next SPI activity occurs with the higher SCLK. This appears to be another slow read at address 0x14. This would represent the next address, but it should also be a clue as to what code is executing because, rather than just continue the slow read without reissuing the command, the code that is running opted to reissue the read command.

    That is, the spi traffic out of the OMAP is

    0x03 0x00 0x00 0x00 (slow read at 0) followed by 4 sets of SCLK to read 4 bytes

    0x03 0x00 0x00 0x04 (slow read at 4) followed by 4 sets of SCLK to read 4 bytes

    0x03 0x00 0x00 0x08 (slow read at 8) followed by 4 sets of SCLK to read 4 bytes

    4 sets of SCLK to continue reading at addresses 0x0c through 0x0f

    4 sets of SCLK to continue reading at addresses 0x10 through 0x13

    <<<<<something bad happens>>>>>>>

    0x03 0x00 0x00 0x14 (slow read at 0x14) followed by 4 sets of SCLK to read 4 bytes

    Now to the questions...

    You would like me to write an infinite loop and execute it. The loop will not have SPI accesses in it. I'm not sure what you want the switch settings to be, but I'm assuming that you want to remove DSPAIS code from the equation. In that case, I would flash my infinite loop as dspais, change the switches to the SPI flash boot setting and run the ROM bootloader again. I believe that the result will be the same as that described above (because I believe DSPAIS never runs.) Is that the scenario you envision?

    Your message suggests that you want to replace the ROM bootloader with the infinite loop, but I don't know how to do that. That is, to the best of my knowledge, the ROM bootloader will run no matter what.

    One possibility is that, you want me to load the infinite loop instead of the spi-flash-writer and that you then will assist me in adding in the code for the ROM bootloader, one little chunk at a time until the spi clock goes nuts. Is this the scenario you envision?

  • I rounded up an old board (with Rev 1 OMAP) to look at the SPI timing on it. I intentionally disconnected the ethernet cable so that u-boot would not successfully boot.

    This is a board that one of our engineers uses regularly, so I believe the boot process works on it (if the ethernet cable is plugged in). All I wanted to do was to verify the "backwards compatibility" of the SPI boot process. I am only interested in the SCLK speed, so I didn't bother hooking up leads to SIMO, SOMI, and chip select.

    Needless to say, the spi traffic bears no resemblance to that captured on the Rev 2 part. For example, I see 4 groups of 5 byte accesses (for a total of 20 bytes) instead of the 3 groups of 8 and 2 groups of 4 followed by the fast accesses. All 20 of the spi accesses have an SCLK frequency of less than 1Mhz. I don't see any traffic after that, so I can't compare the behavior of the 33rd byte access.

    The SPI clock for the first several bytes on the Rev 2 OMAP occurred with a SCLK of about 10 MHz, so something has changed.

  • We need a dump of the first 32 bytes of your boot image (0x00-0x20 of the flash).  There is obviously an AIS command in that region that is causing different behavior on rev1 parts versus rev2 parts. Can't think what it could be, but we will know it when we see it.

    Regards, Daniel

  • I'm assuming that "boot image" means dspais. An output of the command "od -cx dsp-spi-ais.bin" follows. Note that I think we have not changed this file from the original distribution that came with the development kit. (I can't find a CCS project for it on my system or in our repository.) The spi-flash-writer project (dsp) says that the offset for dspais is 0, so I'm assuming it is stored at offset 0 in the SPI flash.

    0000000   T   I   P   A   c   Y   S   X  \r   Y   S   X 001  \0 001  \0
            4954 4150 5963 5853 590d 5853 0001 0001
    0000020  \0  \0  \0  \0 004   Y   S   X 001   Y   S   X  \0  \0 001 200
            0000 0000 5904 5853 5901 5853 0000 8001
    0000040  \0 022  \0  \0 366 024 275 001 333   Y 020  \0   )   H 221 001
            1200 0000 14f6 01bd 59db 0010 4829 0191
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            002b 0388 dc45 9ce5 00e9 01c0 1713 3000
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            0200 e200 1fda 0210 c2f5 21bc 0029 0288
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            0eea 0380 ac45 0626 e268 0280 0277 220c
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            0000 e800 22f4 01fc cccd dc4d 4c6e 6246
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    0001440 001  \0     346 347 002 020   " 220 005  \0   0 021 246 001   
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            005a 37bd 2c6e 0c6e 42e4 01bc 0028 0207
    0002100  \0  \0  \0 342  \0   @  \0  \0   t 242  \f 002   = 314   n   l
            0000 e200 4000 0000 a274 020c cc3d 6c6e
    0002120   d   "  \r 002   n   l   " 002   t   "  \r 002   M 334   n   l
            2264 020d 6c6e 0222 2274 020d dc4d 6c6e
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            9f10 0ffe 004d 0627 4162 0186 fc5d 9ccd
    0006540  \0  \0 340 352   n   l 305 206 315 234   ] 334   n   L   A   &
            0000 eae0 6c6e 86c5 9ccd dc5d 4c6e 2641
    0006560 311 216 305 234   !   a 371   / 346   "   < 002 020 233 376   /
            8ec9 9cc5 6121 2ff9 22e6 023c 9b10 2ffe
    0006600   @  \0 340 341 344 002 020   " 346 322 274 001  \0   `  \0  \0
            0040 e1e0 02e4 2210 d2e6 01bc 6000 0000
    0006620   b 243 214  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0
            a362 008c 0000 0000 0000 0000 0000 0000
    0006640  \0  \0  \0  \0   w   5   w 205   *   \ 021 002 352  \0   @ 002
            0000 0000 3577 8577 5c2a 0211 00ea 0240
    0006660   M 020   o 002   b 201 205 001   (  \0 221 001 350  \0 300 001
            104d 026f 8162 0185 0028 0191 00e8 01c0
    0006700  \0  \0   0 341   d 002  \f  \0   * 002 221 002 352  \0 300 002
            0000 e130 0264 000c 022a 0291 00ea 02c0
    0006720   n   ,   G 220 220  \b  \0 320   B 234 024 005 346   4   ( 302
            2c6e 9047 0890 d000 9c42 0514 34e6 c228
    0006740 200  \0  \0 341   F   D   n   ,   n  \f   o 002   b 201 203 001
            0080 e100 4446 2c6e 0c6e 026f 8162 0183
    0006760   Y 340   +  \0 240 341   + 005   ! 201 004 300 346   4   ( 302
            e059 002b e1a0 052b 8121 c004 34e6 c228
    0007000  \0  \0   ` 340   b 003 020 300   (   F 221 001 350  \0 300 001
            0000 e060 0362 c010 4628 0191 00e8 01c0
    0007020   d 002  \f  \0   )   D 221 321 022  \b  \0 320   c 023  \0 300
            0264 000c 4429 d191 0812 d000 1363 c000
    0007040  \0  \0 020 340 350  \0 300 321   d 002  \f 320  \0   @  \0  \0
            0000 e010 00e8 d1c0 0264 d00c 4000 0000
    0007060   b 001 204 001   (   D 221 001 350  \0 300 001   d 002  \f  \0
            0162 0184 4428 0191 00e8 01c0 0264 000c
    0007100  \0   @  \0  \0  \0  \0  \0  \0   )   ^ 221 321 022 006  \0 320
            4000 0000 0000 0000 5e29 d191 0612 d000
    0007120   c 023  \0 300 350  \0 300 321   d 002 214 321  \0   @  \0  \0
            1363 c000 00e8 d1c0 0264 d18c 4000 0000
    0007140   b 001 210 001   (   ^ 221 001 350  \0 300 001   d 002 214 001
            0162 0188 5e28 0191 00e8 01c0 0264 018c
    0007160  \0   @  \0  \0  \0  \0  \0  \0   b 023  \f  \0   b 201 207 001
            4000 0000 0000 0000 1362 000c 8162 0187
    0007200 022   t  \0 020     241  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0
            7412 1000 a120 0000 0000 0000 0000 0000
    0007220  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0
            0000 0000 0000 0000 0000 0000 0000 0000
    0007240  \0  \0  \0  \0 367   %   w 225 307   e   w   %   Y 352 023  \0
            0000 0000 25f7 9577 65c7 2577 ea59 0013
    0007260   N   F   F   @   #   !   @ 300   e 002   ( 320 240 006 200  \0
            464e 4046 2123 c040 0265 d028 06a0 0080
    0007300 202  \0   ` 341   X 243 004 200 250 377 377 241 350 377 377 241
            0082 e160 a358 8004 ffa8 a1ff ffe8 a1ff
    0007320 331 017 200 221 272  \n   n 214 021 030  \0  \0   X 200   ( 005
            0fd9 9180 0aba 8c6e 1811 0000 8058 0528
    0007340  \0 200  \0 342   d   6   ( 002   n   L 306 301 316   e  \a 225
            8000 e200 3664 0228 4c6e c1c6 65ce 9507
    0007360   b 001 204 001   x   ` 251 001   X 340 214 001   X 017 017 005
            0162 0184 6078 01a9 e058 018c 0f58 050f
    0007400   8  \0 300 340   d   6   (  \0   n   l 352 034 020 020  \0 300
            0038 e0c0 3664 0028 6c6e 1cea 1010 c000
    0007420   d   6   ( 302   F   `   n   , 250 377 377 001 350 377 377 001
            3664 c228 6046 2c6e ffa8 01ff ffe8 01ff
    0007440  \0 200   @ 342   X 352 017  \0 352   F   F       d 002  \f 320
            8000 e240 ea58 000f 46ea 2046 0264 d00c
    0007460 332 037  \f 225   X 243 004 200 333 037  \0 220 372 006   n 214
            1fda 950c a358 8004 1fdb 9000 06fa 8c6e
    0007500  \f 200   @ 350   o  \0   n   l   b 001 202 001 346   2   (  \0
            800c e840 006f 6c6e 0162 0182 32e6 0028
    0007520   n   l 253  \0   b 003  \0       n   l 207   e   w   e 357 001
            6c6e 00ab 0362 2000 6c6e 6587 6577 01ef
    0007540  \0 250     355 346   3   < 005 344   R 274 005  \0   `  \0  \0
            a800 ed20 33e6 053c 52e4 05bc 6000 0000
    0007560  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0
            0000 0000 0000 0000 0000 0000 0000 0000
    0007600  \0  \0  \0  \0 361   ) 030  \0 241   G 230  \0   X 243 004 004
            0000 0000 29f1 0018 47a1 0098 a358 0404
    0007620 245   6 220 301   ) 001  \0 304 330 037 220 004 247   V 220 202
            36a5 c190 0129 c400 1fd8 0490 56a7 8290
    0007640   %  \n 245 204 243   y 030  \0 240 207 030 001 265   7 020 250
            0a25 84a5 79a3 0018 87a0 0118 37b5 a810
    0007660   V 242   N 024   Z 243 204  \0 245   7 220   # 243 341 003   
            a256 144e a35a 0084 37a5 2390 e1a3 2003
    0007700 300  \0  \0 341 332   h  \0 001   c 003  \f   ` 247   7 220   (
            00c0 e100 68da 0100 0363 600c 37a7 2890
    0007720   Z 340 003       5   6 224 301   C   @ 200 300 307   R   o 330
            e05a 2003 3635 c194 4043 c080 52c7 d86f
    0007740  \0 020  \0 350   7   V 224 202 264   * 210 204   U   7 024 250
            1000 e800 5637 8294 2ab4 8488 3755 a814
    0007760 330 017      \0   u   7 224 303 240 341 003 300 001 200 203  \0
            0fd8 0020 3775 c394 e1a0 c003 8001 0083
    0010000   v   7 224 310 244   7 220 003  \0   @  \0  \0  \0  \0  \0  \0
            3776 c894 37a4 0390 4000 0000 0000 0000
    0010020 001   @ 003  \0   t   7 224 003   b 243 214  \0  \0  \0  \0  \0
            4001 0003 3774 0394 a362 008c 0000 0000
    0010040  \0  \0  \0  \0   Z  \0 277  \a   ' 006   E 334   ] 334   E 254
            0000 0000 005a 07bf 0627 dc45 dc5d ac45
    0010060   n   L   I 276   { 005   n 214   n  \f 301   &   E 334   ] 334
            4c6e be49 057b 8c6e 0c6e 26c1 dc45 dc5d
    0010100  \0 200 300 357   n   l   I 276 220 376 377   /   n 214 357 201
            8000 efc0 6c6e be49 fe90 2fff 8c6e 81ef
    0010120   Z  \0 275  \a   Z  \0 277  \a   E 254   n  \f 366   B   <  \0
            005a 07bd 005a 07bf ac45 0c6e 42f6 003c
    0010140  \0  \0 240 344 300  \t 023 002 332 032 020  \0 022 001  \0   
            0000 e4a0 09c0 0213 1ada 0010 0112 2000
    0010160 300 311 020   " 332 032 020  \0   n   L  \r 334   b 203 214  \0
            c9c0 2210 1ada 0010 4c6e dc0d 8362 008c
    0010200  \0  \0  \0 344   Z  \0 275  \a  \0  \0  \0  \0  \0  \0  \0  \0
            0000 e400 005a 07bd 0000 0000 0000 0000
    0010220  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0
            0000 0000 0000 0000 0000 0000 0000 0000
    0010240  \0  \0  \0  \0 367   1   & 006 022   4 377 037   E 254   G 022
            0000 0000 31f7 0626 3412 1fff ac45 1247
    0010260 246   % 023 003   (  \0     003 347   R 274   1 220  \t  \0   0
            25a6 0313 0028 0320 52e7 31bc 0990 3000
    0010300 363  \0 240 341 220   q 377   /   j  \0   @ 003 330 017  \f   2
            00f3 e1a0 7190 2fff 006a 0340 0fd8 320c
    0010320   *  \0 020 002   b 003  \f   0   b 001 206 001 367   q 246 005
            002a 0210 0362 300c 0162 0186 71f7 05a6
    0010340  \0  \0  \0 350 330 017  \f 002  \0      \0  \0   b 003  \f  \0
            0000 e800 0fd8 020c 2000 0000 0362 000c
    0010360  \0 200  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0
            8000 0000 0000 0000 0000 0000 0000 0000
    0010400  \0  \0  \0  \0   * 376 220  \a 352  \0 300  \a 362  \t 277  \a
            0000 0000 fe2a 0790 00ea 07c0 09f2 07bf
    0010420   *  \0  \0  \a 352  \0   @  \a   *   @  \a 002 352  \0   @ 002
            002a 0700 00ea 0740 402a 0207 00ea 0240
    0010440   b 003 020  \0   (   ` 021 002   b   A 203 001 350  \0   @ 002
            0362 0010 6028 0211 4162 0183 00e8 0240
    0010460   ( 300 210 001 350  \0 300 001  \0  \0  \0  \0   b 023  \f  \0
            c028 0188 00e8 01c0 0000 0000 1362 000c
    0010500   b 201 210 001   * 300 006 002 352  \0   @ 002   b 003 020  \0
            8162 0188 c02a 0206 00ea 0240 0362 0010
    0010520   b   a 205 001   X 243 004 002     241 005  \0  \0  \0  \0  \0
            6162 0185 a358 0204 a120 0005 0000 0000
    0010540  \0  \0  \0  \0 367   T 274 001 022 220 376 037   F 002   * 006
            0000 0000 54f7 01bc 9012 1ffe 0246 062a
    0010560 346   R 274 301 020 350 377 337  \0   @  \0  \0   b 003  \f 300
            52e6 c1bc e810 dfff 4000 0000 0362 c00c
    0010600     200 200 340   b 001 201 001 220 355 376 017 346   R 274 001
            8020 e080 0162 0181 ed90 0ffe 52e6 01bc
    0010620  \0   `  \0  \0  \0 200  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0
            6000 0000 8000 0000 0000 0000 0000 0000
    0010640  \0  \0  \0  \0 250 377 377 002 351 377 377 002   * 240 210 002
            0000 0000 ffa8 02ff ffe9 02ff a02a 0288
    0010660 353  \0 300 002   ' 376 351 226 306   b 357 002   e 002  \f   2
            00eb 02c0 fe27 96e9 62c6 02ef 0265 320c
    0010700  \0 006  \0 346   X 243  \0 002   X 243 200 001   X 200 224   1
            0600 e600 a358 0200 a358 0180 8058 3194
    0010720  \0  \0  \0  \0 332 037  \f 002  \0  \0  \0  \0  \0  \0  \0  \0
            0000 0000 1fda 020c 0000 0000 0000 0000
    0010740  \0  \0  \0  \0   b 243 214  \0  \0  \0  \0  \0  \0  \0  \0  \0
            0000 0000 a362 008c 0000 0000 0000 0000
    0010760  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0
            0000 0000 0000 0000 0000 0000 0000 0000
    0011000  \0  \0  \0  \0  \0  \0  \0  \0     241 001  \0  \0  \0  \0  \0
            0000 0000 0000 0000 a120 0001 0000 0000
    0011020  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0  \0
            0000 0000 0000 0000 0000 0000 0000 0000
    0011040  \0  \0  \0  \0 001   Y   S   X 030   # 001 200   L  \0  \0  \0
            0000 0000 5901 5853 2318 8001 004c 0000
    0011060 200  \0  \0   $ 300 377 377   $ 201  \0  \0   $ 301  \0  \0   $
            0080 2400 ffc0 24ff 0081 2400 00c1 2400
    0011100 202 341  \0 365 202 340  \0 345  \0  \0  \0   y  \0  \0  \0  \0
            e182 f500 e082 e500 0000 7900 0000 0000
    0011120  \a  \0  \0 352 376 377 377 352 376 377 377 352 376 377 377 352
            0007 ea00 fffe eaff fffe eaff fffe eaff
    0011140 376 377 377 352 376 377 377 352 376 377 377 352 376 377 377 352
            fffe eaff fffe eaff fffe eaff fffe eaff
    0011160  \0  \0  \0  \0  \f  \0 037 345  \0 360 240 341 001   Y   S   X
            0000 0000 000c e51f f000 e1a0 5901 5853
    0011200   d   # 001 200      \0  \0  \0 024 004 001 200   L 004 001 200
            2364 8001 0020 0000 0414 8001 044c 8001
    0011220   t 004 001 200   ` 004 001 200   t 004 001 200   t 004 001 200
            0474 8001 0460 8001 0474 8001 0474 8001
    0011240   t 004 001 200   j 004 001 200 001   Y   S   X 300   " 001 200
            0474 8001 046a 8001 5901 5853 22c0 8001
    0011260   T  \0  \0  \0 004  \0  \0  \0  \0   " 001 200  \0  \0  \0  \0
            0054 0000 0004 0000 2200 8001 0000 0000
    0011300  \0  \0  \0  \0 004  \0  \0  \0 210   " 001 200  \0  \0  \0  \0
            0000 0000 0004 0000 2288 8001 0000 0000
    0011320  \0  \0  \0  \0 004  \0  \0  \0 214   " 001 200  \0  \0  \0  \0
            0000 0000 0004 0000 228c 8001 0000 0000
    0011340  \0  \0  \0  \0 004  \0  \0  \0 270   " 001 200 300 021 001 200
            0000 0000 0004 0000 22b8 8001 11c0 8001
    0011360  \0  \0  \0  \0 004  \0  \0  \0 274   " 001 200 300 021 001 200
            0000 0000 0004 0000 22bc 8001 11c0 8001
    0011400  \0  \0  \0  \0  \0  \0  \0  \0 006   Y   S   X 340 020 001 200
            0000 0000 0000 0000 5906 5853 10e0 8001
    0011420

     

  • Flamingo said:

    I'm assuming that "boot image" means dspais. An output of the command "od -cx dsp-spi-ais.bin" follows. Note that I think we have not changed this file from the original distribution that came with the development kit. (I can't find a CCS project for it on my system or in our repository.) The spi-flash-writer project (dsp) says that the offset for dspais is 0, so I'm assuming it is stored at offset 0 in the SPI flash.

    0000000   T   I   P   A   c   Y   S   X  \r   Y   S   X 001  \0 001  \0
            4954 4150 5963 5853 590d 5853 0001 0001
    0000020  \0  \0  \0  \0 004   Y   S   X 001   Y   S   X  \0  \0 001 200
            0000 0000 5904 5853 5901 5853 0000 8001

    The 3rd through 5th words of the AIS image are setting the prescalar of the SPI module to 0, which is not a supported setting of the SPI module.  The prescalar should be 0x2 or higher (the ROM defaults the value to 0x0E).  Why this is causing the exact timing issue you are seeing, I can't say exactly.  As a workaround, try updating the dspais image so that the fifth word of the image (at offset 0x10) is not 0x00000000, but rather 0x0000000E.  Alternatively, you can remove the third, fourth, and fifth words entirely.  Then reflash the image to the SPI flash and try booting.

    We will need to report this issue with the dspais file to the appropriate team, assuming that the workaround mentioned above fixes the problem.

    Regards, Daniel

  • I found the dspubl project and even found where the prescaler was set. I changed it and rebuilt, but the generated code was .out, not .bin. I downloaded the AISgen tool. That is where things started to fall apart. The instructions said to type

    hexgen -romid D800K001 -seqread -crc 1 -spiclk 0 -appln <PATH to ubl-spi.out or ubl-nand.out> -output <dsp-spi-ais.bin or dsp-spi-ais.bin>

    in the directory of the installation.

    I tried that, but "hexgen" is not recognized. If the files in that directory, I tried "HexAIS_OMAP-L137.exe", which seemed like the likely choice. It does not understand the "-romid". I read the help and formatted the command:

    HexAIS_OMAP-L137.exe -otype binary -o dsp-spi-ais.bin <input file>

    It gave me the error "No ini file provided. Using default. OMAP-L137.ini

    File OMAP-L137.ini not found.

    I'm not sure where to go from here. Can you point me to an AISgen tool installation that provides the hexgen executable? Or a different tool to convert the .out to .bin?


  • My intention was not for you to rebuild the dsp-spi-ais file, but rather just edit the binary you already had.  That hexgen command line is from the tools that were originally distributed for the version 1.0 ROM.  The HexAIS tool is distributed for the new ROM revision.

    If you want an INI file, use the following content:

    <begin INI file>

    ; General settings that can be overwritten in the host code
    ; that calls the AISGen library.
    [General]

    ; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW
    BootMode=SPIMASTER

    ; 8,16,24 - used for SPI,I2C
    AddrWidth=24         

    ; NO_CRC,SECTION_CRC,SINGLE_CRC
    crcCheckType=SECTION_CRC


    [AIS_SeqReadEnable]

    ; This section lets us configure the peripheral interface
    ; of the current booting peripheral (I2C, SPI, or UART).
    ; Use with caution. The format of the PERIPHCLKCFG field
    ; is as follows:
    ; SPI:        |------24|------16|-------8|-------0|
    ;             |           RSVD           |PRESCALE|
    ;
    ; I2C:        |------24|------16|-------8|-------0|
    ;             |  RSVD  |PRESCALE|  CLKL  |  CLKH  |
    ;
    ; UART:       |------24|------16|-------8|-------0|
    ;             | RSVD   |  OSR   |  DLH   |  DLL   |
    [PERIPHCLKCFG]
    PERIPHCLKCFG = 0x0000000E

    <end INI file>

     

    I would still recommended simply editing the binary you have as indicated in the previous post.

    Regards, Daniel

  • I understood your intent, but I'm not sure what tool to use to edit the .bin file. Is your suggestion that I put a breakpoint in the spi-flash-writer code and edit the buffer after I've read the record? If so, is there a CRC or checksum that I would have to edit? I would certainly have to edit the buffer again when I run the verify step (which I've modified to perform a real verify).

  • Use a hex editor. See here for a list of available programs.  I personally use TinyHexer on Windows.

    Regards, Daniel

  • Didn't work, but I'm comparing the data to the hex dump I gave you. There is byte swap going on, so that the SPI bytes are 0x5449, 0x5041, etc. The last byte is 0x0E, but should it be the next-to-last-byte?

    The SPIFMT0 is still 0x00020008 after the processor hangs, suggesting that the prescaler is still 0.

  • In byte order, an AIS file will appear as follows:

    So based on your earlier post, yes I believe there is some ordering issue you may need to overcome (depending on what program you are using to edit and view the binary contents). Note that the above was generated using the ini data I provided in the earlier post, in conjunction with the HexAIS tool for OMAP-L137.

    Regards, Daniel

  • Okay, thanks. I reproduced that and the SPI clock stays a normal speed. Unfortunately, the code still doesn't boot. 'm not sure if I have a similar problem with the armubl or if the reads from the SPI are giving me corrupt data. I'm working on that. (If you know of any similar magic byte for armubl, please let me know.)

     

  • Two questions:

    1. Does armubl have a similar SPI CLK prescaler stored in a location that I can view?

    2. I tried to follow the AISgen directions that I found online (http://processors.wiki.ti.com/index.php/Flashing_the_C6747#Generating_Boot_Script_.28AIS_image.29), but the instructions don't match the files I downloaded from the link on the page. (I have files AISgen.exe and HexAIS_OMAP-L137.exe.) Could you give me the instructions that would work with the version downloaded from the link? Or could you post the correct link/instructions?