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How does the C6474/C6472 SRIO peripheral handle rapid doorbells arrivals

Hi

If an external device (say FPGA for example) sends multiple doorbells with the same info field to the DSP's SRIO peripheral,

a) are they input to the same Rx FIFO as data packets and dealt with sequentially?

b) how many doorbells with the same info field can be received before a doorbell retry is sent back to the FPGA?

c) how many doorbells each with a different info field can be received before a doorbell retry is sent back to the FPGA?

I'm guessing that  in b), the sending device keeps getting a doorbell retry message from the DSP until the DSP clears the bit in DOORBELLx_ICCR. True?

If the above is true, then the DSP's SRIO peripheral can only handle one doorbell at a time when the info bits are the same.

Cheers

  • Eddie,

    a) are they input to the same Rx FIFO as data packets and dealt with sequentially?

    Yes, but to clarify, the doorbells are received sequentially and handled in order with respect to data packets in the RX physical layer.  Once they are handed to the logical layer for processing, they are handled by the same protocol unit (MAU) that processes the incoming directIO packet types. i.e. NWRITE, NWRITE_R, SWRITE, NREAD.  For these packet types, the doorbells will be processed in order with the data packets.  There is even a built-in hardware function that makes sure all preceeding data packets have landed in memory before the doorbell actually sets an interrupt ICSR bit, this avoids any race conditions.

    b) how many doorbells with the same info field can be received before a doorbell retry is sent back to the FPGA?

    For our DSPs, incoming doorbell info fields are decoded to set one interrupt ICSR bit , i.e. there is a one-to-one encoding of info field to ICSR bit.  There is no FIFO per bit.  So, if a doorbell is decoded and the ICSR bit is already set, we retry the doorbell.  This is explained in the SRIO user's guide, interrupt section.

    c) how many doorbells each with a different info field can be received before a doorbell retry is sent back to the FPGA?

    There are 64 ICSR bits, so you could effectively send 64 doorbells with different info fields and never get a retry - even if the receiving DSP never clears any of the ICSR bits.  It should be pointed out that our RX decode of the doorbell info field is fixed, so although there is 16 bits available in the info field, we only allow 6 bits to be set, i.e. 2 bits decide the register, and 4 bits decide the ICSR bit that is set.  If any of the reserved bits are set, we error respond.  This is described in the user's guide in more detail.

     

    I'm guessing that  in b), the sending device keeps getting a doorbell retry message from the DSP until the DSP clears the bit in DOORBELLx_ICCR. True?

    If the above is true, then the DSP's SRIO peripheral can only handle one doorbell at a time when the info bits are the same.

    Yes, you are correct.  Hope that helps.

    Regards,

    Travis

     


  • Hi Travis

    Thanks for the information. It really helps to clear things up.

    tscheck said:
    So, if a doorbell is decoded and the ICSR bit is already set, we retry the doorbell.  This is explained in the SRIO user's guide, interrupt section.

    This info eludes me. I grepped the dock for "retry" and the hits I get are in the Message Passing protocol with the CPPI. Where does it state this for the Direct I/O operation?

    (I am looking in sprue13h - C6472 SRIO users guide)

    Cheers

  • Eddie,

    Looks like it is not there after all.  I've requested that it be added to the user's guide in the interrupt section.

     

    Should read...

    The DOORBELL packet's 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers (see Table 23 for assignment of the 16 bits of DOORBELL_INFO field). Each bit can be assigned to any core as described by the Interrupt Condition Routing Registers. Additionally, each status bit is user-defined for the application. For instance, it may be desirable to support multiple priorities with multiple TID circular buffers per core if control data uses a high priority (for example, priority = 2), while data packets are sent on priority 0 or 1. This allows the control packets to have preference in the switch fabric and arrive as quickly as possible. Since it may be required to interrupt the CPU for both data and control packet processing separately, separate circular buffers are used, and DOORBELL packets must distinguish between them for interrupt servicing. If any reserved bit in the DOORBELL info field is set, an error response is sent. If the DOORBELL info field indicates an interrupt bit (ICSR) which is already set, a retry response is sent.

     

    Regards,

    Travis

  • Thanks Travis