EMIFA Clockout issue

Hi,

We are looking into your request and we will update you shortly.

Thanks for your patience.

Regards,
Sivaraj K

Pramod,

Is all other functionalities working fine in the board ?

What do you mean by EMIFA clock output is partially getting generated ?

Please share the scope capture of EMIFA clock output at pin V28 ?

Regards,
Senthil

Hello Senthil,

Thanks for reply,

All 4 DSP's are getting POR and able to target 4 DSP's is CCS v5 using emulator,

Able to launch the target configuration and initialize C6457.gel file,

EMIFA clock is been generated but P-P swing is less compared with working board,

Please find the attached scope capture of EMIFA clock output at pin V28,

Also find the attached working board scope capture of EMIFA clock output at pin V28. Board8_EMIFA.zip

Thanks,

Pramod

Pramod,

what is the issue you are facing on EMIF interface ?

What was the problem you faced on the DVDD33 voltage rail ? Any short to the ground ? The clock signals does not meet the voltage requirements. It seems like the internal IO is damaged as it does not able to swing to its full level. Do you see any issue on other signals ?

Regards,
Senthil

Hello Senthil,

Thanks for reply,

Actually in our design we are interfacing EMIFA to FPGA for data transfers,

We have enabled all DSP's to EMIFA boot mode,

We are using PTH08000WAH module for powering DVDD33 voltage rail,

Frequently PTH08000WAH module and respective circuitry is getting damaged,there is no short to ground,

please let us know if any script file is available for data write/read in CCS for EMIFA interface to conclude that internal IO is damaged?

Thanks,

Pramod

Pramod,

I would like you sort out the power supply issue first. Please follow my recommendations in other thread.

Please check below link for EMIF example code.

www.ti.com/.../toolssoftware

Regards,
Senthil