C6455 SRIO 1port 4 lane directIO operation failed

Hi,

    I'm now designing with C6455 SRIO. On my board, there are one TMS320C6455 and one FPGA (xcv5sx50t) connected by 4x SRIO. The refclk is from a 156.25MHz LVDS oscillator fanout to these two devices.

    I've got SRIO directIO operation worked well at 3.125GHz 1p1x. But when I change it to 1p4x--simply change register SP0_CTL[31:30] from 00 to 01 which is the default value of the register field "PORT_WIDTH", the SRIO directIO operation fails. It seems like the PHY  initialization is OK, but at the FPGA end, there is no data recieved.
    Below is the output of the attached ccs project. (And there's some thing maybe help: the frist 7 lines print out slowly, the 8th and following lines print out fast.)

Run 1000 times to analyze the SRIO transfer......
please wait......
wlsu_reg6 = 0rlsu_reg6 = 2  FAIL: SRIO transfers number 0
wlsu_reg6 = 0rlsu_reg6 = 2  FAIL: SRIO transfers number 1
wlsu_reg6 = 0rlsu_reg6 = 2  FAIL: SRIO transfers number 2
wlsu_reg6 = 0rlsu_reg6 = 2  FAIL: SRIO transfers number 3
wlsu_reg6 = 0rlsu_reg6 = 2  FAIL: SRIO transfers number 4
wlsu_reg6 = 0rlsu_reg6 = 2  FAIL: SRIO transfers number 5
wlsu_reg6 = 0rlsu_reg6 = 2  FAIL: SRIO transfers number 6
wlsu_reg6 = 14rlsu_reg6 = 14  FAIL: SRIO transfers number 7
wlsu_reg6 = 14rlsu_reg6 = 14  FAIL: SRIO transfers number 8
wlsu_reg6 = 14rlsu_reg6 = 14  FAIL: SRIO transfers number 9
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Any help / suggestion would be greatly appreciated!