2 PCIe unit in loop back mode for single c6670 ?

Hi,

For my understanding, your test method is not possible on C66xx device. I have tested PCIe PHY loopback on C6678 EVM board, the same initialization steps are enough for C6670 device. Please take a look at below similar e2e links.

Thanks,

thanks,

and if I'll wire the PCIe on my board cross over, is the test method possible ?

Hi Ganapathi,

I tried to run the file that you attached for back loop PHY:

e2e.ti.com/.../2086.pcie_5F00_sample.txt

it has written "ltssm = 0x11" and stopped, waiting for response from EP.....

I run also the same program in EP mode on the Core1, and in the RC mode on the Core0, but it also not worked.

Is it some properties that I have to get it work?

Hi,

PHY loopback mode does not required physical connect between PCIe transmit and receive signals, we nee to skip Detect state in LTSSM and force link to begin with POLL_ACTIVE state. If you skip this step the PHY loopback is not configured. After link up LTSSM_STATE goes to DETECT_QUIET state.

PCie PHY loopback works on RC mode only. Please try to run the default PCie PHY loopback code on core0 and compare your test logs with my output console log.

Thanks,

done.

my steps:

1)load GEL fille.

2) Load program with loop back on core 0. My output:

the core send the info, but did not get it back, and wiat for it in while. 

**********************************************
* PCIe Test Start *
* RC mode *
**********************************************

Version #: 0x01000003; string PCIE LLD Revision: 01.00.00.03:Nov 19 2012:16:16:30

Power domain is already enabled. You probably re-ran without device reset (which is OK)
PCIe Power Up.
PLL configured.
Successfully configured Inbound Translation!
Successfully configured Outbound Translation!
Configure PHY Loopback...
Starting link training...
Force PCIe Link state...
Debug0 Value #: 0x0081f3d8

LTSM Value #: 11

Link is up.

///////////////////////////////////////////////////////////////////////////////////////////

This is my constants (I did  not change anything)

/* Size of application buffers */
#define PCIE_BUFSIZE_APP 40

/* Write pattern */
#define PCIE_WR_PATTERN 0xFACEFACE

/* In this example all addresses are 32bit */
/* Outbound Base Address for PCIe Master */
#define PCIE_OB_LO_ADDR_M 0x70000000
#define PCIE_OB_HI_ADDR_M 0

/* Inbound Base Address for PCIe Master */
#define PCIE_IB_LO_ADDR_M 0x90000000
#define PCIE_IB_HI_ADDR_M 0

/* Outbound Base Address for PCIe Slave */
#define PCIE_OB_LO_ADDR_S PCIE_IB_LO_ADDR_M
#define PCIE_OB_HI_ADDR_S 0

/* Inbound Base Address for PCIe Slave */
#define PCIE_IB_LO_ADDR_S PCIE_OB_LO_ADDR_M
#define PCIE_IB_HI_ADDR_S 0

/* BAR mask */
#define PCIE_BAR_MASK 0x0FFFFFFF

/* BAR Index PCie*/
#define PCIE_BAR_IDX_M 1
#define PCIE_BAR_IDX_S 1

/* PCIe Regions used in the example */
#define PCIE_IB_REGION_M 0
#define PCIE_OB_REGION_M 0
#define PCIE_IB_REGION_S 0
#define PCIE_OB_REGION_S 0

Thanks for your update.