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DM816x M3 memory test

David Soto - RidgeRun
Genius 3700 points

Hi,

    We are using the DM816x and the EZSDK 5.05.02.00, the unit is basically doing H264 encoding through OMX for hours without stopping the encoding session. We are seeing a random behaviour where suddenly the board stops processing frames. We believe that the problem appears only when the HDVICP2 (encoder) is added to the equation likely because it exercises more the RAM

   I was reading another e2e post where Badri states that it could be caused by DDR memory bit flip, is there a tool to stress the memory from the M3 side? How can we verify if the problem is a bit flip?

Thanks,,

-David

[1] e2e.ti.com/.../903492

  • 0
    TI__Guru**** 170625 points

    Hi David,

    I read the e2e thread that you are pointing to, and I see that lowering the DDR3 frequency from 1600MHz to 800MHz improves stability. This means that the byte wise SW leveling should be made, in order to achieve optimal stability in higher DDR3 frequency.

    Based on the call flow it looks like there is a bit flip in DDR memory causing the crash.

    Are you always seeing same assert or do you see random failures. I would expect random failures if it is DDR memory bit flip.

    If you have not done any changes in mcfw links looks like there is a board issue which is causing DDR memory corruption.

    -- Make sure all the steps in are followed and you have done byte wise s/.w leveling correctly.

    -- CHeck if reducing DDR frequency improves stability.

    -- Check there is no voltage ripple on DDR 1V constant supply.

    -- Do DDR memory stress test for atleast a couple of days on entire memory range.

    You cannot just use the macro values on your board, You should do the s/w leveling procedure and modify the uboot to use the obtained DQS etc, values.Also try with AVS disabled and constant 1.05 V supply to eliminate any issue due to board power supply ripple.

    Our DDR3 frequency is 1333, but we overclocked to 1600.

    I've tested DDR 800 no problem.