MIPS measurement of MPEG1 L2 decoder is higher than expected

David,

   Can you please confirm if you are using the same cache configuration (32Kbytes L1P, 16Kbytes L1D and  64Kbytes of L2) on DA830 board as well? MIPS number looks high on DA830. ON DM644x, both program and data are placed on DDR2. I think DA830 has SRAM, which will show some increment with MIPS numbers(should not be more than 10% for MP3 decoder) 

thanks,

Venkat  

I am using the default DSK DA830 GEL file:

..\..\emulation\boards\dskda830\gel\dskda830_dsp.gel

It configures L1 as 32kB L1P, and 32kB L1D. (There is only 64 kB L1)

The 256 kB L2 is not explicitly configured. I know that the xdc/runtime/knl/Cache functions return true when called, but now looking at the L2CFG register says that the cache is disabled. Perhaps this is the problem. What is the common way to enable it when using RTSC and DSP/BIOS 6? Is the GEL file the best place to do it?

The relevant lines in the .cfg file for DSP/BIOS 6 are:

var Cache             = xdc.useModule('xdc.runtime.knl.Cache');
Cache.Proxy = xdc.useModule('ti.sysbios.xdcruntime.CacheSupport');

The DA830 uses SDRAM instead of DDR2 RAM, and all code and data is loaded into the SDRAM.

Thanks for your help.

David Kelly

I have confirmed that the the high MIPS is due to the L2 cache being disabled.

When I enable the L2 cache to 256 kB by manually editing the L2CFG register before executing the program, I get ~17 MHz which agrees with the datasheet.

I still have the question as to the best means for configuring the cache in DSP/BIOS 6. I do not see the API in the Cache kernel module.

Thanks David Kelly