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[C6655, PCIe] Generating test pattern for compliance test

Naoki Kawada
Guru 19890 points

Hello, 

My customer is planing to generate test pattern for compliance test in order to check if the eye specification matches the requirement on their target board.
I suggested the customer to do the following register configurations to generate test pattern:

  • When LTSSM is in L0/L0s/L1 state, setup Link Control Register 2 (LINK_CTRL2)
    - ENTR_COMPL = 1 to invoke compliance test
    - TGT_SPEED = 1 to invoke 2.5GT
  • Port Link Control Register (PL_LINK_CTRL)
    RST_ASRT = 1 to move LTSSM to Hot Reset state

From my understanding, that is all required configuration. If I'm missing something, please let me know.
And another question is the register configuration for PL_LINK_CTRL.RST_ASRT after the completion of compliance test. From my understanding, LTSSM would go to Detect state. At this point, Should we manually de-assert PL_LINK_CTRL.RST_ASRT (i.e., PL_LINK_CTRL.RST_ASRT = 0) for further processing ? Or, can we keep this bit-filed as is ?

Best Regards,
Naoki 

  • 0
    TI__Guru* 95265 points
    This is not documented. We need to check and feed back to you.Regards, Eric
  • 0 in reply to lding
    TI__Guru* 95265 points

    There are two threads for this:

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/383448/1351663

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/371984/1320913#1320913

    Looks simply program those two registers didn't work. We did PCIE compliance test with PCI SIG – The DUT transmitter is connected to a standard load board and a high-bandwidth sampling scope running a standard pcie test script is used to observe the transmitter electrical performance under a variety of conditions.

    Regards, Eric

  • 0 in reply to lding
    TI__Guru* 95265 points

    From PCIE spec:

    Link Control 2 Register, bit 4: Enter Compliance – Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by setting this bit to 1b in both components on a Link and then initiating a hot reset on the Link. Default value of this bit following Fundamental Reset is 0b.

    For completeness:

    From SW side: Need to setup target speed and de-emphasis, then set enter compliance bit, then set RST_ASRT bit.

    From HW side: PCI SIG – The DUT transmitter is connected to a standard load board, which bring the PCIe signals to SMP connector so they can be connected to the scope for compliance measurement, to observe the transmitter electrical performance under a variety of conditions.

    The RST_ASRT bit needs to be cleared after test.

    To be safe, I would recommend separating the compliance test and function test and not mixing them. Do the compliance to check signal quality, and then do a system reset, and switch to functional mode.

    Regards, Eric