OMAPL138 UPP init sequence

In chapter 2.6.1 of sprugj5 it is mentioned that after setting the SWRST bit in UPPCR to 1 we have to wait at least 200 device clock cycles before resetting the bit again. What is meant by device clock cycles? Is this the upp clock (150MHZ), the cpu clock (300MHZ) or the oscillator clock (24MHZ)?

Thanks so far...