What would cause RRDY not to go high when there is good line activity on the McBSP?
Details : I'm using McBSP0, and generating CLKR and FSR. I open my McBSP, configure it, and start it. I see nice CLKR and FSR waveforms reading my ADC. I see data on DSR coming from my ADC. My logic analyzer decodes it nicely. Yet RRDY never goes high! When I call the following function, it hangs on the while() loop forever.
Uint32 MCBSP_sentry_read32( MCBSP_Handle hMcbsp ){
// Wait for read to be ready
while( ! MCBSP_rrdy( hMcbsp ) );
// Read it in
return MCBSP_read32( hMcbsp );
}
I configure it like so...
jj_test_config.spcr1 = 1 << 13; /* Sign extend and right-justify */
jj_test_config.spcr2 = 1 << 9 | 3 << 6; /* Sample rate generator enabled.*/
jj_test_config.xcr1 = 0;
jj_test_config.xcr2 = 0;
jj_test_config.rcr1 = 5 << 5; /* Received word length... 32 bit transactions */
jj_test_config.rcr2 = 1 << 2 | /* Frame sync error ignore. */
1; /* 1 Bit of data delay. Data starts clock after the FS. */
jj_test_config.srgr1 = 23; /* CLKDVG of 23 */
jj_test_config.srgr2 = 1 << 13 | /* CLKSM = 1 for internal McBSP clock*/
33; /* FPER of 34 - 1*/
jj_test_config.pcr = 0x0F00; //1 << 10 | 1 << 8; // | 1 << 2; /* Turn on Frame sync from internal. DRCLK driven out..*/
MCBSP_config( mhMcbsp, &jj_test_config ); MCBSP_start( mhMcbsp, MCBSP_RCV_START | MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 33 ); // Turn on interrupts globally IRQ_globalEnable();
Then I just read it in a loop, but RRDY is never high? What's broken here? Am I missing some subtlety?
Thanks.
