How to configure configure SPI0 in am335x as a master module?

Hi,

Which SDK version are you using?

Best Regards,
Yordan

Hi,
Thanks for your reply.

I don't think I am using SDK.
In fact, I want to configure it in lower layer and write my own C code as the following steps:
1. Hard or soft reset.
2. Read MCSPI_SYSSTATUS.
3. Check if reset is done.
4. Module configuration: (a) Write into MCSPI_MODULCTRL (b) Write into MCSPI_SYSCONFIG.
5. Channel Configuration: Write MCSPI_CH(i)CONF.
6. Start the channel: Write 0000 0001h in MCSPI_CH(i)CTRL.
7. First write request: TX empty - Generate DMA write event/ polling TX empty flag by CPU to write First
transmit word into MCSPI_TX(i).
8. End of transfer: Stop the channel by writing 0000 0000h in MCSPI_CH(i)CTRL
which are provided from the document "am335 technical reference manual.pdf".

And the flowing context is my C code, could you please help me to have a check?
The symbol like "MCSPI_MODULCTRL" is a define about the corresponding register offset address,
and symbol like "SPI_MODULCTRL_MS" is a define about the corresponding bit in a register.
And I am sure the address offset is correct.

Main initial:
void spi1_init(void){
clock_init();//bus clock initial
spi_control_mode_init();//spi mode initial

read_spi0_revision(MCSPI_REVISION);//to read the spi revision

if(spi0_softreset(MCSPI_SYSCONFIG)){// to have a soft reset
cprintf("software reset done.\n");
}

MCSPI_MODULCTRL_configure(MCSPI_MODULCTRL);//to configure the register MCSPI_MODULCTRL

MCSPI_SYSCONFIG_configure(MCSPI_SYSCONFIG);// to configure the register MCSPI_SYSCONFIG

MCSPI_SYST_configure(MCSPI_SYST);//to conifgure the register MCSPI_SYST

MCSPI_CH0CONF_configure(MCSPI_CH0CONF);// to configure the register MCSPI_CH0CONF

enable_channel0(MCSPI_CH0CTRL);// to enable channel 0
}
And the corresponding functions:
//to configure the register MCSPI_MODULCTRL
void MCSPI_MODULCTRL_configure(unsigned int offset){
unsigned int MODULCTRL = SPI0_read_register((void *)offset);//read
MODULCTRL &= ~SPI_MODULCTRL_INITDLY_6; //no delay
MODULCTRL &= ~SPI_MODULCTRL_INITDLY_5; //no delay
MODULCTRL &= ~SPI_MODULCTRL_INITDLY_4; //no delay
MODULCTRL &= ~SPI_MODULCTRL_MS; //master
MODULCTRL |= SPI_MODULCTRL_PIN34; //pin-3
MODULCTRL |= SPI_MODULCTRL_SINGLE; //single channel
SPI0_write_register((void *)offset,(unsigned int)MODULCTRL);//write
MODULCTRL = SPI0_read_register((void *)offset);
cprintf("MODULCTRL = 0x%x\n",MODULCTRL);
}
// to configure the register MCSPI_SYSCONFIG
void MCSPI_SYSCONFIG_configure(unsigned int offset){
unsigned int SYSCONFIG = SPI0_read_register((void *)offset);//read
SYSCONFIG |= SPI_SYSCONFIG_CLOCKACTIVITY_H; //OCP and Functional clocks maintained
SYSCONFIG |= SPI_SYSCONFIG_CLOCKACTIVITY_L;
SPI0_write_register((void *)offset,(unsigned int)SYSCONFIG);//write
SYSCONFIG = SPI0_read_register((void *)offset);
cprintf("SYSCONFIG = 0x%x\n",SYSCONFIG);
}
//to conifgure the register MCSPI_SYST
void MCSPI_SYST_configure(unsigned int offset){
unsigned int SYST = SPI0_read_register((void *)offset);//read
SYST &= ~SPI_SYST_SPIENDIR; //SPIEN output
SYST &= ~SPI_SYST_SPIDATDIR1; //D1 output (MOSI)
SYST |= SPI_SYST_SPIDATDIR0; //D0 input (MISO)
// SYST |= SPI_SYST_SPICLK; //CLKSPI line drive high
// SYST |= SPI_SYST_SPIDAT_1; //SPIDAT1 drive high
SYST |= SPI_SYST_SPIEN_0; //SPIEN0 drive high
SPI0_write_register((void *)offset,SYST);//write
SYST = SPI0_read_register((void *)offset);
cprintf("SYST = 0x%x\n",SYST);
}
// to configure the register MCSPI_CH0CONF
void MCSPI_CH0CONF_configure(unsigned int offset){
unsigned int CH0CONF = SPI0_read_register((void *)offset);
cprintf("CH0CONF = 0x%x\n",CH0CONF);
CH0CONF &= ~SPI_CHOCONF_CLKG; //clock granularity of power of 2
CH0CONF &= ~SPI_CHOCONF_TRM_H; //transmission and reception mode
CH0CONF &= ~SPI_CHOCONF_TRM_H; //transmission and reception mode
CH0CONF &= ~SPI_CHOCONF_IS; //select D0 for reception
CH0CONF &= ~SPI_CHOCONF_DPE1; //select D1 for transmission
CH0CONF |= SPI_CHOCONF_DPE0; //No transmission on D0
// CH0CONF |= SPI_CHOCONF_DMAR; //enable DMAR
// CH0CONF |= SPI_CHOCONF_DMAW; //enable DMAW
CH0CONF |= SPI_CHOCONF_WL_9; //the spi word is 8-bits long
CH0CONF |= SPI_CHOCONF_WL_8; //the spi word is 8-bits long
CH0CONF |= SPI_CHOCONF_WL_7; //the spi word is 8-bits long
CH0CONF &= ~SPI_CHOCONF_EPOL; //SPIEN is held high during the active state
CH0CONF &= ~SPI_CHOCONF_CLKD_5; //Clock divide by 64
CH0CONF |= SPI_CHOCONF_CLKD_4; //Clock divide by 64
CH0CONF |= SPI_CHOCONF_CLKD_3; //Clock divide by 64
CH0CONF &= ~SPI_CHOCONF_CLKD_2; //Clock divide by 64
CH0CONF |= SPI_CHOCONF_POL;
CH0CONF |= SPI_CHOCONF_PHA; //Mode 3

CH0CONF |= SPI_CHOCONF_FORCE; //SPIEN high

SPI0_write_register((void *)offset,CH0CONF);
CH0CONF = SPI0_read_register((void *)offset);
cprintf("CH0CONF = 0x%x\n",CH0CONF);
}
// to enable channel 0
void enable_channel0(unsigned int offset){
unsigned int CH0CTRL = SPI0_read_register((void *)offset);
CH0CTRL |= SPI_CHOCTRL_EN;
SPI0_write_register((void *)offset,CH0CTRL);
CH0CTRL = SPI0_read_register((void *)offset);
cprintf("CH0CTRL = 0x%x\n",CH0CTRL);
}



Best,
Zefeng