Custom IBL fails to run properly on custom C6678 board

ABDULKERIM ALTUNTAS

Other Parts Discussed in Thread: TMS320C6678

Hello,

We have a custom C6678 DSP board derived from the EVM C6678 board. Actually both boards have a lot in common but there are differences between them, too. The major difference is in the DDR3_CLKIN and the SGMII-SRIO_SERDES_CLKIN oscillator frequencies. Having these in mind, we encounter strange problems in properly running IBL. We use MCSDK_2_01_02_06. Below we put the steps that we have gone through so far:

* Due to the differences between our custom board and the EVM, we were required to modify the IBL source code to suit for our board.

* So we examined the IBL source code and modified the necessary parts. We did not alter the flow of the code, we just made some parametric changes like modifying the DDR3-PLL divider.

* After these modifications, we downloaded MinGW and we were able to re-build the IBL following the IBL build instructions included in the MCSDK folder.

* One of the outputs of the IBL build is the binary file which is to be written to the EEPROM.

* We utilized the eepromwriter program found in the MCSDK, and wrote the binary IBL file to the EEPROM without error. That is, all the write, read and verify steps in the eemprowriter program passed.

* We then switched to I2C-Boot mode and powered-up our custom board.

* Referring to the IBL source code, we understand that IBL runs in two stages: ibInit() and iblMain()

* iblInit() seems to run properly and the program branches to the iblMain() function. Following it, we observe that the IBL version string gets printed on the UART port.

* Up to the deviceDdrConfig() function everything seems to work without problem.

* However, in the deviceDdrConfig() function, somehow the program crashes.

* We do not know the exact line where the crash occurs since we cannot connect to Core-0 through the XDS560V2 emulator. If we try to connect it, we get the error “Device core was hung...”. This means that Core-0 still tries to run something but we don’t know what.

* In contrast,if we comment-out the deviceDdrConfig() line in the iblMain(), IBL runs correctly and tries to boot from TFTP as intended. We see the prints on the UART port.

NOTE:

The modifications that we did in the IBL code, are also implemented in the platform_init() function in PDK. Our custom platform_init() function runs seamlessly on our custom board. So we believe that the problem that we face is not directly related to the modifications.

Could anyone help us with this problem?

Thanks.

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

Hi,

Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

We will get back to you on the above query shortly. Thank you for your patience.

0 Raja over 9 years ago

TI__Guru* 81335 points

Hi,
I recommend you to run the platfom_test available in PDK on custom board to verify the platfom init happens correctly.

Thank you.

0 ABDULKERIM ALTUNTAS over 9 years ago in reply to Raja

Prodigy 200 points

Hi Rajasekaran,

Thank you for tour quick reply.

As you recommended, except the NAND and NOR flash tests, we ran all the tests found in the platform_test on our custom board. The tests that we conducted passed with no problems. Below we put the test configuration:

platform_test_input.txt:

init_pll = 1
init_ddr = 1
init_uart = 1
init_tcsl = 1
init_phy = 1
init_ecc = 1

print_info = 1
print_current_core_id = 1
print_switch_state = 1
test_eeprom = 1
test_nand = 0
test_nor = 0
test_led = 1
test_uart = 1
run_external_memory_test = 1
run_internal_memory_test = 1

init_config_pll1_pllm = 0
init_config_uart_baudrate = 115200

nand_test_block_number = 1000
nor_test_sector_number = 10
led_test_loop_count = 1
led_test_loop_delay = 2000000
ext_mem_test_base_addr = 0x80000000
ext_mem_test_length = 0x1fffffff
int_mem_test_core_id = 2

Followings are the logs that we got during the tests:

p_info->version = 1.00.00.00
p_info->cpu.core_count = 8
p_info->cpu.name = TMS320C6678
p_info->cpu.id = 21
p_info->cpu.revision_id = 0
p_info->cpu.silicon_revision_major = 0
p_info->cpu.silicon_revision_minor = 0
p_info->cpu.megamodule_revision_major = 8
p_info->cpu.megamodule_revision_minor = 1
p_info->cpu.endian = 1
p_info->board_name = CUSTOM_BOARD
p_info->frequency = 1000
p_info->board_rev = 0
p_info->led[PLATFORM_USER_LED_CLASS].count = 4
p_info->led[PLATFORM_SYSTEM_LED_CLASS].count = 0
p_info->emac.port_count = 2
EMAC port 1 connected to the PHY.
MAC Address = 00:17:ea:cf:65:af

EEPROM Device (@ 0x50):
p_device->device_id = 80
p_device->manufacturer_id = 1
p_device->width = 8
p_device->block_count = 1
p_device->page_count = 1
p_device->page_size = 65536
p_device->spare_size = 0
p_device->handle = 80
p_device->flags = 0
p_device->bboffset = 0

EEPROM Device (@ 0x51):
p_device->device_id = 81
p_device->manufacturer_id = 1
p_device->width = 8
p_device->block_count = 1
p_device->page_count = 1
p_device->page_size = 65536
p_device->spare_size = 0
p_device->handle = 81
p_device->flags = 0
p_device->bboffset = 0
Current core id is 0
User switch 1 state is ON
UART test start
Open a serial port console in a PC connected to
the board using UART and set its baudrate to 115200
You should see following message ---
This is a Platform UART API unit test ...
Type 10 characters in serial console
Char 0 = a
Char 1 = b
Char 2 = c
Char 3 = d
Char 4 = e
Char 5 = f
Char 6 = g
Char 7 = h
Char 8 = i
Char 9 = j
UART test complete
EEPROM test start
test_eeprom: passed
EEPROM test complete
LED test start
LED 0 ON
LED 0 OFF
LED 0 ON
LED 1 ON
LED 1 OFF
LED 1 ON
LED 2 ON
LED 2 OFF
LED 2 ON
LED 3 ON
LED 3 OFF
LED 3 ON
LED test complete
Internal memory test start
Internal memory test (for core 2) passed
Internal memory test complete
External memory test start
External memory test passed
External memory test complete
Test completed

We didn't ran the NAND Test because we don't have a NAND Flash on our board. The NOR Flash on our board is connected to EMIF16 port. As a result we couldn't run the NOR Test either since the NOR driver present in the PDK is SPI based. However, we tested the NOR Flash with our custom driver based on EMIF16, and we know that the NOR Flash works as desired.

What's your suggestion?

Thank you.

Sincerely,
Abdulkerim

0 Rogerio Almeida over 9 years ago in reply to ABDULKERIM ALTUNTAS

TI__Mastermind 26205 points

I am escalating...sorry for the delay....

0 dzhou over 9 years ago in reply to Rogerio Almeida

TI__Genius 9065 points

Hello,

Independent of IBL, did you test your DDR to make sure the setting works?

There is a simple DDR test that is part of the C6678 GEL, it is called ddr3_memory_test () and you can control the start and end address of the space. I'd modify the GEL to fit your board and then run this test to make sure it works first. Then make sure same setting were used for IBL DDR config.

regards

David

0 ABDULKERIM ALTUNTAS over 9 years ago in reply to Rogerio Almeida

Prodigy 200 points

No problem Rogerio.

Thanks,

Abdulkerim

0 ABDULKERIM ALTUNTAS over 9 years ago in reply to dzhou

Prodigy 200 points

Hello David,

Last week we solved the problem. As you all suggested our issue was related to the DDR3 configuration settings.

Actually before we ran into the custom IBL problem, we had already successfully implemented our settings in both the GEL file and the platform library. Both of them were tested and verified including the ddr3_memory_test(). However, in the DDR3 PLL settings of the IBL configuration structure, I did a mistake and I modified postdiv instead of prediv. As a result the DDR3 Memory Controller tried to operate at 1000MHz!! Because of this, the DDR3 Memory Controller could not operate properly -in my opinion the controller gets completely out of order- causing Core-0 to stall indefinetely as soon as the program tries to read/write some of the DDR3 Memory Controller registers. By correcting the mistake, now IBL seems to work properly including DDR3.

Thank you,

Regards

0 Raja over 9 years ago in reply to ABDULKERIM ALTUNTAS

TI__Guru* 81335 points

We are glad that the issue has been solved. Thank you for the update.

0 Rogerio Almeida over 9 years ago in reply to Raja

TI__Mastermind 26205 points

Team,

thanks so much.

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Custom IBL fails to run properly on custom C6678 board