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PCIe Demo Locks up on AM5728 EVM

Other Parts Discussed in Thread: AM5728

I am trying to run the project PCIE_idkAM572x_wSocLib_C66BiosExampleProject on our TMDXEVM5728.

First step was to change the board type in the file "C:\ti6\pdk_am57xx_1_0_0\packages\ti\drv\pcie\example\sample\am572x\c66\bios\pcie_sample_wSoCLib.cfg".  I changed Board.Settings.boardName = "evmAM572x"; and compiled the project.  I loaded and ran the project via the XDS560 JTAG.  It always gets stuck in the following function at the yellow highlighted for loop.  The value of shift is a huge number.  Now, if I set a break point at the red highlighted line, the value of shift is 8.  That seems reasonable.  If I then single step the code it jumps to the line in blue and the value of shift is 0x3F51E000. The stack shows that __c6xabi_divull() is called from BoardCtrlPadMux().   I've tried stepping the assembly code and it looks like at some point the memory location of shift is being overwritten.  The assembly lines that seem to do the overwrite are here:

8000f704:   06B3EDA1            SHR.S1        A12,0x1f,A13
8000f708:   023C23C6 ||         STDW.D2T2     B5:B4,*+B15[1]

/***********************************************************************/

/* */

/* _divull() - Unsigned 64-bit division. */

/* */

/***********************************************************************/

#ifdef __TI_EABI__

_CODE_ACCESS unsigned long long __c6xabi_divull(unsigned long long x1, unsigned long long x2)

#else

_CODE_ACCESS unsigned long long _divull(unsigned long long x1, unsigned long long x2)

#endif

{

register int i;

register unsigned long long num;

register unsigned long long den;

register int shift;

unsigned long long first_div = 0;

unsigned long long num64;

shift = _lmbdull(1, x2) - _lmbdull(1, x1);

if (x1 < x2) return 0;

if (x1 == 0) return 0;

/* ! if (x2 == 0) return -1; */

if (x2 == 0) return (unsigned long long) -1;

num = x1;

den = x2 << shift;

num64 = (_lmbdull(1, x1) == 0);

first_div = num64 << shift;

if (den > num) first_div >>= 1;

if (num64)

{

if(den > num) { den >>= 1; num -= den; }

else { num -= den; den >>= 1; }

}

else

shift++;

for (i = 0; i < shift; i++)

{

num = _subcull(num, den);

}

if (shift)

return num << (64-shift) >> (64-shift) | first_div;

else

return first_div;

}

  • I will forward this to the RTOS team.
  • Oh, I forgot to mention that this is called from pcie_sample.c->main()->Board_init(boardCfg). So, it is never making it to the PCIe demo code.
  • May I know your setup? You are using  GP EVM or IDK or your customized board? What card is RC and EP?

    Regards, Eric

  • GP EVM 5728

    The code does not get out of Board_Init() so whether I am RC or EP does not really matter now.

    Perhaps the problem is with the boot mode of the GP EVM. It currently boots off the SD Card into the Linux based demo. Should I remove the SD Card so it does not boot when trying to run this C66 demo on the DSP? Maybe the ARM and DSP are having a conflict of some kind.
  • I used the attached .txt file to create a CCS project. The file calls the attached .cfg with board type as Board.Settings.boardName = "evmAM572x"; I have no issue to run it as RC mode and detect a mini-PCIE wifi card.

    I didn't use SD card/Linux. Just connect the A15 core within 8 seconds, then enable the DSP1 clk via GEL, load the .out to DSP and run. Maybe there is conflict when Linux run first.

    Regards, Ericpcie_sample_wSoCFile_evm.cfg

    -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/soc/am572x/src/pcie_soc.c"
    -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/src/pcie_sample.c"
    -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/am57x/src/pcie_sample_board.c"
    -ccs.linkFile "PDK_INSTALL_PATH/ti/drv/pcie/example/sample/am572x/c66/bios/pcie_sample_wSocFile_evm.cfg"
    -ccs.setCompilerOptions " -mv6600 -g -DSOC_AM572x --diag_warning=225 -I${PDK_INSTALL_PATH}/ti/drv/pcie/example/sample/src -I${PDK_INSTALL_PATH}/ti/drv/pcie/example/sample/am57x/src" -rtsc.enableRtsc
    
     

  • I guess I don't quite understand how this works. If I power up the EVM without an SD card, it shuts itself off in 6 seconds. I can't get CCS to connect via the XDS560 to the A15 that quickly. The GEL file starts running but the EVM shuts off before it completes. I've tried all the boot modes and it powers off after 6 seconds. I've also inserted the jumper in J5 as directed in the document AM572x General Purpose EVM HW User Guide.


    IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.
    IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset.
    IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset.
    IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.
    IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.
    CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<---
    CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
    CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
    CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz
    CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz
    CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
    CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
    CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
    CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
    CS_DAP_PC: Error connecting to the target: (Error -180 @ 0x0) The controller has detected a target power loss. The user must turn-on or connect the power supply for the target. (Emulation package 6.0.83.0)
    IcePick_D: Power Failure on Target CPU
    CS_DAP_DebugSS: Power Failure on Target CPU: (Error -180 @ 0x0) The controller has detected a target power loss. The user must turn-on or connect the power supply for the target. (Emulation package 6.0.83.0)
  • Also, assuming we get the A15 to connect, are you loading the DSP via a GEL file via the A15 or are you connecting to the DSP via JTAG and loading that way? (I'd prefer the connection to the DSP method.)
  • I got the debugger to connect by changing the JTAG TCLK Frequency to "Automatic with faster 35.0 MHz".

    Once connected to the A15, I executed the GEL Script "AM527X MULTICORE Initialization -> DSP1SSCLKEnable_API"

    I made sure my project matched as directed above.

    I still have the same exact issue.  Code gets stuck in the for loop with a huge shift value.  However, I guess I was just impatient.  It takes 18 seconds to get out of Board_Init() function.  That can't be right.  

    Can you please confirm how long it takes to execute the Board_Init() function?

  • Christopher,

    Sorry for the pain to connect to AM572x GP EVM, the steps is documented at processors.wiki.ti.com/.../AM572x_GP_EVM_Hardware_Setup. As the PMIC shut the board off in 7 seconds, it really needs very fast speed to connect to A15. Then, run GEL for DSP11SSClkEnable_API as you did.

    Below is my log from CCS:

    Cortex_M4_IPU1_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
    Cortex_M4_IPU1_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
    Cortex_M4_IPU1_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
    Cortex_M4_IPU1_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
    Cortex_M4_IPU2_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
    Cortex_M4_IPU2_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
    Cortex_M4_IPU2_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
    Cortex_M4_IPU2_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
    C66xx_DSP1: GEL Output: --->>> AM572x C66x DSP Startup Sequence In Progress... <<<---
    C66xx_DSP1: GEL Output: --->>> AM572x C66x DSP Startup Sequence DONE! <<<---
    C66xx_DSP2: GEL Output: --->>> AM572x C66x DSP Startup Sequence In Progress... <<<---
    C66xx_DSP2: GEL Output: --->>> AM572x C66x DSP Startup Sequence DONE! <<<---
    CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<---
    CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<---
    CortexA15_1: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<---
    CortexA15_1: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<---
    IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.
    IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset.
    IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset.
    IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.
    IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.
    CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<---
    CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
    CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
    CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz
    CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz
    CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
    CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
    CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
    CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
    CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
    CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<---
    CortexA15_0: GEL Output: --->>> I2C Init <<<---
    CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<---
    CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<---
    CortexA15_0: GEL Output: --->>> AM572x PG1.1 GP device <<<---
    CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
    CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress...
    CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking...
    CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE!
    CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress...
    CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE!
    CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress...
    CortexA15_0: GEL Output: PER DPLL already locked, now unlocking
    CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE!
    CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress...
    CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking....
    CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE!
    CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress...
    CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE!
    CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress...
    CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE!
    CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress...
    CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE!
    CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress...
    CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE!
    CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress...
    CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE!
    CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
    CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
    CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
    CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
    CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress...
    CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE!
    CortexA15_0: GEL Output: Launch full leveling
    CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers
    CortexA15_0: GEL Output: as per HW leveling output
    CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from
    CortexA15_0: GEL Output: PHY_STATUSx registers
    CortexA15_0: GEL Output: Launch full leveling
    CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers
    CortexA15_0: GEL Output: as per HW leveling output
    CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from
    CortexA15_0: GEL Output: PHY_STATUSx registers
    CortexA15_0: GEL Output: Two EMIFs in interleaved mode - (2GB total)
    CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
    CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!! <<<---
    CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
    CortexA15_0: GEL Output: DEBUG: Clock is active ...
    CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
    CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
    CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---

    After that, load the PCIE program to DSP1, then change PcieModeGbl to RC depending on your setup and run. I didn't experience any delay for calling through Board_init().

    I am attaching a pre-build out file for your reference. This file has:

    #define IO_CONSOLE

    So, only below flag is enabled on boardCfg:

    boardCfg = BOARD_INIT_UNLOCK_MMR

    And the results are printed in CCS console. The out file has already set the card as PCIE RC and has a little bit my debug code inside, when run it gives me:

    [C66xx_DSP1] **********************************************

    * PCIe Test Start *

    * RC mode *

    **********************************************


    Version #: 0x02020002; string PCIE LLD Revision: 02.02.00.02:Oct 7 2015:14:42:32


    PlatformPCIESS1 ClockEnable

    PlatformPCIESS/21PllConfig

    PlatformPCIESS1CtrlConfig

    PlatformPCIESS1Reset

    PlatformPCIESS1PhyConfig

    PCIe Power Up.

    PLL configured.

    Successfully configured Inbound Translation!

    Successfully configured Outbound Translation!

    Starting link training...

    Link is up.

    RC side 0x51002104 = 0x45 and 0x51000080 = 0x30110008

    EP sending interrupts to RC

    Regards, Eric

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/PCIE_5F00_evmAM572x_5F00_wSoCFile_5F00_C66BiosExampleProject.out

  • So, you are not running the example as is provided in the distribution which is why you don't see the same issue I see. In the distribution, #define IO_CONSOLE is commented out. This causes BOARD_INIT_PINMUX_CONFIG to be or'ed into boardCfg which is what ultimately causes the big delay in the function I noted above. I believe there is a bug of some kind in that function which caused a memory overwrite and corruption of the shift variable. Once I uncommented the IO_CONSOLE define in pcie_sample.h the code executed without delay as did your test code.

    You must also have another difference in your project versus the distribution as I do not see the following printouts in the Console when I run the distribution example nor do I see in the code where those would come from.

    PlatformPCIESS1 ClockEnable
    PlatformPCIESS/21PllConfig
    PlatformPCIESS1CtrlConfig
    PlatformPCIESS1Reset
    PlatformPCIESS1PhyConfig

    I would very much like it if you could run the example as distributed and see if you then see the same issue I started this thread about.
  • In reference to the comment,

    "Sorry for the pain to connect to AM572x GP EVM, the steps is documented at processors.wiki.ti.com/.../AM572x_GP_EVM_Hardware_Setup. As the PMIC shut the board off in 7 seconds, it really needs very fast speed to connect to A15. Then, run GEL for DSP11SSClkEnable_API as you did."

    I followed the steps in that document exactly as written.  The problem was we had a different XDS pod which had a slower TCLK.  Maybe some mention of the required TCLK for proper operation should be added to the wiki page.

  • Yes,

    I tried the distribution as it is, with UART to printout the log. It takes ~20 seconds to execute through Board_init() routine. And in RC mode, I can't enumerate the EP. While with the distribution if I only #define IO_CONSOLE, that is to use CCS to print info, there is no delay and enumeration happens (RC mode). I will report this to developer.

    The previous out file I uploaded has some small debug print I added (I mentioned already).

    Regards, Eric

  • Awesome, thanks.
  • An update on this.  If I skip over the BOARD_INIT_PINMUX_CONFIG then I can't get the UART to work.  So, I guess I am stuck with the 18 second delay for now.  Please advise if a fix is found.

  • Can you please check if there is a plan to update the code for this issue?

  • So, on a wild hair I decided to try this again with the new Processor SDK for AM5728 (2.0.1) and the new code gen tools, 8.1.0. Problem remains. The function BoardCtrlPadMux runs for about 18 seconds stuck in a loop in _c6xabi_divull with a bogus shift value on line 140 of imath64.c. Any word on if this is planned to be fixed or can we get a work around?
  • Peter,

    The latest fixes for C66x alignment issue in Processor SDK 2.0.2 (to be released any time this week) should help remove the 20 second problem.

     

    Regards, Eric

  • Yes, the problem seems to be gone. Thanks.