DM8148 and SYNCTIMER32K documentation

2.1 Reading the counter

The counter register is a 32-bit “atomic datum” and his 16-bit capture is done on the 16-bit LSB first to allow atomic LSB16 + MSB16 capture.

3. REGISTERS DESCRIPTION

Bit width : 32 bits. ( Can be 32bits or 2 x16 bits)

Address of one register : Start address + Offset address.

3.1 Register Mapping

All the registers are:

*32-bit register accessible in 16-bit mode.
*little endian addressing.

Register Name Size Access Address Offset
LSB MSB
32KSYNCNT_REV 32-bit Read 0x00 0x02
Reserved 0x04 0x06
Reserved 0x08 0x0A
Reserved 0x0C 0x0E
CR 32-bit Read 0x10 0x12

3.2 Identification register (32KSYNCNT_REV)
This read-only, 32-bit register (accessible in 16-bit mode) contains the hardware revision number of the module. A write to this register has no effect.

[7:0] CID_REV Module HW revision number, value at reset: HW ID revision
[31:8] Unused

This CID_REV field indicates the revision number of the current timer module. This value is fixed by hardware.
The Least significant 4-bit LSBs of CID_REV indicate a minor revision.
The Most significant 4-bit of CID_REV MSBs indicate a major revision.
The reset value is:
0x11 =>: version 1.1

A reset has no effect on the value returned.

3.3 Counter Register (CR) (Read) little endian addressing
The CR register is a 32-bit register. So the MPU performs a 32-bit access on the register while the DSP performs two consecutives 16-bit transactions. Also, note that since the Ocp is completely asynchronous with the clk_32KHz, some synchronization is done, so as to make sure that the CR value is not read while it is being incremented.
In 16 bits mode the following sequence must be followed to read the CR register properly:

a) Perform an OCP Read Transaction to Read the lower 16-bit of the CR register (offset = 10). When the CR is read and synchronized, the lower 16-bit ‘LSB’ are driven onto the “ocp_sdata” bus and the Upper 16-bit of the CR ‘MSB’ register are stored in a Temporary register.
b) Perform an OCP Read Transaction to Read the upper 16-bit of the CR register (offset = 12). During this Read, the value of the upper 16-bit ‘MSB’ that has been temporary register is forwarded onto the “ocp_sdata” bus.

So, to read the value of CR correctly, the first OCP read access has to be to the lower 16-bit (i.e. offset = 10), followed by OCP read access to the upper 16-bit (i.e., offset= 12).