AM335x/RTOS: Using EDMA with the MMCSD controller

Hi,

There is a new release of the RTOS SDK: software-dl.ti.com/.../index_FDS.html

Unfortunately, that is already what I am using. The PROCESSOR-SDK-RTOS-AM335X 02_00_00_00 includes pdk_am335x_1_0_0 as one of its directories.

One thing that looks suspicious to me is the following snippet of code where the driver is configuring the PaRAM set for a receive buffer:

	            /* Src is in INCR mode & Dest is in FIFO modes                        */
	            paramSet.opt &= MMCSD_EDMA3CC_OPT_DAM_INCR_MODE;
	            paramSet.opt |= MMCSD_EDMA3CC_OPT_SAM_CONST_MODE;

	            /* FIFO width is 8 bit                                                */
	            paramSet.opt &= MMCSD_EDMA3CC_OPT_FIFO_WIDTH;

Is the FIFO width actually correct?  Here is the rest of the PaRAM setup for reference:

	            /* Get the PaRAM set for default parameters                               */
	            EDMA3_DRV_getPaRAM((EDMA3_DRV_Handle) hwAttrs->edmaHandle,
	                                    (uint32_t) hwAttrs->rxDmaEventNumber, &paramSet);

	            /* Fill the PaRAM Set with transfer specific information */
	            paramSet.destAddr  = (uint32_t)(object->dataBufIdx);

	            paramSet.srcAddr = (uint32_t) ((hwAttrs->baseAddr)
	                             + CSL_MMCHS_DATA);

	            /**
	            * Be Careful !!!
	            * Valid values for SRCBIDX/DSTBIDX are between –32768 and 32767
	            * Valid values for SRCCIDX/DSTCIDX are between –32768 and 32767
	            */
	            paramSet.aCnt       = 4;
	            paramSet.bCnt       = (uint16_t) (transaction->blockSize / 4);
	            paramSet.srcBIdx    = 0;
	            paramSet.srcCIdx    = 0;

	            paramSet.destBIdx   = 4;
	            paramSet.destCIdx   = transaction->blockSize / 4;

	            /* For AB-synchronized transfers, BCNTRLD is not used. */

	            paramSet.linkAddr   = 0xFFFFu;

	            paramSet.bCntReload = (uint16_t) 0;

	            /* Src is in INCR mode & Dest is in FIFO modes                        */
	            paramSet.opt &= MMCSD_EDMA3CC_OPT_DAM_INCR_MODE;
	            paramSet.opt |= MMCSD_EDMA3CC_OPT_SAM_CONST_MODE;

	            /* FIFO width is 8 bit                                                */
	            paramSet.opt &= MMCSD_EDMA3CC_OPT_FIFO_WIDTH;

	            /* EDMA3_DRV_SYNC_AB                                                  */
	            paramSet.opt &= MMCSD_EDMA3CC_OPT_SYNC_MASK_VALUE;
	            paramSet.opt |= MMCSD_EDMA3CC_OPT_SYNC_AB;

	            /* EDMA3_DRV_OPT_FIELD_TCINTEN                                        */
	            paramSet.opt |= ((uint32_t) 1U << MMCSD_OPT_TCINTEN_SHIFT);

	            /* ADDED FOR ARM PLATFORM                                             */
	            /* update the transfer completion code                                */
	            paramSet.opt &= (~MMCSD_EDMA3CC_OPT_TCC_MASK);
	            paramSet.opt |= (( hwAttrs->edmaRxTCC) << MMCSD_EDMA3CC_OPT_TCC_SHIFT);

	            result = EDMA3_DRV_setPaRAM(hwAttrs->edmaHandle, hwAttrs->rxDmaEventNumber, &paramSet);

Again this is cut and pasted from MMCSDDMA_v1.c.

I'm starting to suspect that the MMCSD controller is not sending all the DMA requests properly for a multiblock transfer. Can anyone confirm that multiblock transfers work over EDMA with the MMCSD?