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Max total DDR3 memory on K2H

RandyP
Guru* 84110 points


What is the max total usable external DDR3 memory that we can put on the two DDR3A/B interfaces?

Boeing would actually like to put 32GB out there, but I doubt that is possible. There are enough address bits to get that far, though, so I would like to get any ideas on how they could do that even if it means paging using some external logic & registers.

So, we have the following questions:

1. Can we put 8GB on DDR3A plus put 2GB on DDR3B? In this case, it looks like 512MB of DDR3B will be aliased to 0x00 6000 0000.

2. What can be done with the available pins to put more DDR3 on the DDR3A memory interface? I have not yet studied the row addressing of these to see if an FPGA could drive the top few lines to implement a paging mechanism, nor do I know if internal refresh by the DDR3 device might be able to handle refreshing the whole thing if we set the refresh rate to a faster rate, for example. Any ideas, even if something for the customer to try that we cannot guarantee?

Thanks for your ideas and help,

Regards,
Randy

  • 0
    TI__Mastermind 43660 points
    Hello Randy,

    I have requested the team to address this thread.

    Regards,
    Senthil
  • 0
    TI__Mastermind 42545 points

    Hi Randy,

    K2H can address 8GB using DDR3A and the DSP/ARM cores can address 2GB using DDR3B. Other system masters can only access 512MB of the DDR3B address space.

    There are a number of reasons why the memory can't be expanded beyond those limits. The biggest limitation is the availability of very dense memory devices. The highest capacity memory device available from Micron is currently a dual-die 16Gb in a x16 package [ed rp]. This device presents two loads to each pin of the data bus which is the limit we can support. Adding extra memories with some kind of external muxing would also require separate leveling which isn't supported by the DDR3 memory controller.

    Other customers that require a denser memory solution have used the HyperLink bus to communicate with the DDR3 memory of additional processors. The K2H could be connected to two K2E components with the two available HyperLink channels, expanding the available memory to 24GB. I don't see any other solution that would be feasible.

    Regards,
    Bill

  • 0 in reply to Bill Taboada
    TI__Guru* 84110 points

    Bill,

    What is the Micron part number for the dual-die device? [and I think you have a typo, that it should be 16Gb in a x16 package, right?]

    Bill Taboada said:
    K2H can address 8GB using DDR3A and the DSP/ARM cores can address 2GB using DDR3B. Other system masters can only access 512MB of the DDR3B address space.

    So between DDR3A and DDR3B, the DSP/ARM can see a total of 10GB of external memory, with the right MMU / MPAX settings being played with. Is that correct?

    Bill Taboada said:
    Other customers that require a denser memory solution have used the HyperLink bus to communicate with the DDR3 memory of additional processors.

    I will suggest this as a workable idea for them, where they could put DDR3 memory on one side of an FPGA and 1 or 2 of the HyperLink's on the other side of the FPGA, to allow access to a bigger array of memory. It would depend on what they need for access speed, but this may be the fastest or only choice for them.

    Since you know the DDR3 protocol better than I do, I would guess there would not be a way to use external static address values for upper row addresses. Too bad.

    Thanks for getting back to me.

    Regards,
    Randy

  • 0 in reply to RandyP
    TI__Mastermind 42545 points

    RandyP said:

    What is the Micron part number for the dual-die device? [and I think you have a typo, that it should be 16Gb in a x16 package, right?]

    The Micron part number for the TwinDie 16Gb part is MT41K1G16DGA-125.

    RandyP said:

    So between DDR3A and DDR3B, the DSP/ARM can see a total of 10GB of external memory, with the right MMU / MPAX settings being played with. Is that correct?

    That is correct.

    Regards,

    Bill

  • 0 in reply to Bill Taboada
    TI__Guru* 84110 points
    Bill,

    Thanks for the update and confirmation. Good news.

    Where in our documentation do you think it would be good to state the 10GB-accessible size, or do you? Maybe we can just state that the DDR3A can address 8GB, then have some other more specific information added for the DDR3B.

    But at least all FAEs will be able to find it here, if we have the right search terms available. I think we do.

    Regards,
    Randy