GPMC Interfacing

Hi,

We are using GPMC interface of AM4379 to connect an FPGA chip in following mode.

1)NOR type Synchronous 16 bit address/data multiplexed memory device(only using AD0- 15)
2)FPGA is connnectd to Chip select 0(base address is 0x00000000)
3)FPGA CLock frequency at 50 Mhz..

In datasheet,it is mentioned that the first 1MB of address space 0x0-0xFFFFF is inaccessible externally.So we used BASE address as 0x00100000.

After initialization, when we tried to read from GPMC interface as follows

value = ((*(volatile unsigned short *)(0x00100000)));    

We are not seeing any activity on GPMC Lines and Processor is getting getting struck at this line . Can you please help us on this?

we initialized the FPGA as follows..

#define FPGA_BASE_ADDRSS 0x00100000

gpmcCfgObj_t fpga_param =
{
0x50000000,
0,
GPMC_CHIP_SEL_0
};

gpmcChipSelTimingParams_t fpga_cs =
{
0x11, //chipSelWrOffTime
0x11, //chipSelRdOffTime
FALSE, //addExtDelay
0x0 //chipSelOnTime

};

gpmcAdvSignalTimingParams_t fpga_adv =
{
0x0, //advAadMuxWrOffTime;
0x0, //advAadMuxRdOffTime;
0x02, //advWrOffTime
0x02, //advRdOffTime
FALSE, //addExtDelay
0, //advAadMuxOnTime
0 //advOnTime
};

gpmcOeWeSignalTimingParams_t fpga_oe =
{
0x11, //writeEnableOffTime
0x03, //writeEnableOnTime
0x0, //oeAadMuxOffTime
0x11, //oeOffTime
FALSE, //addExtDelay
0x0, //oeAadMuxOnTime
0x03 //oeOnTime
};
gpmcReadAccessTime_t fpga_rd =
{
0x11, //readCycleTime
0x11, //writeCycleTime
0x10, //readAccessTime
0x00, //pageBurstAccessTime
};

gpmcCycle2CycleDelay_t fpga_cycle =
{
1,
GPMC_CYCLE_DELAY_SAME_CHIP_SEL_DELAY,
GPMC_CYCLE_DELAY_DIFF_CHIP_SEL_DELAY,
0
};

gpmcCfgObj_t *pGpmcinit;

/* ========================================================================== */
/* Function Definitions */
/* ========================================================================== */

int32_t ConfigFpga(void)
{
int32_t status = S_PASS;
/*initialize GPMC module instance */
status = InitGpmc();
if(status == S_PASS)
{
/*initialize FPGA */
status= InitFpga();
}

return status;
}

int32_t InitGpmc(void)
{
int32_t status = S_PASS;
pGpmcinit = &fpga_param;
/*initialize clock for GPMC Module*/
status = PRCMModuleEnable(CHIPDB_MOD_ID_GPMC, 0U, 0U);

if(status == S_PASS)
{
/* PinMux Configuration */
status = PINMUXModuleConfig(CHIPDB_MOD_ID_GPMC, 0U,
NULL);
}

return status;
}

int32_t InitFpga(void)
{
int32_t status = S_PASS;
int16_t value;
volatile int32_t timeOut;
int i;
timeOut =0xFFFF;

/*Reset GPMC Module*/
GPMCModuleReset(pGpmcinit->gpmcBaseAddr);

/*Check reset done or not*/
while((GPMCIsModuleResetDone(pGpmcinit->gpmcBaseAddr) != 1) && (timeOut != 0))
{
timeOut--;
}
if(timeOut == 0)
{
return (FALSE);
}

GPMCSetIdleMode(pGpmcinit->gpmcBaseAddr, GPMC_IDLE_MODE_NO_IDLE);

/* Disable all interrupts */
GPMCIntrDisable(pGpmcinit->gpmcBaseAddr, GPMC_INTR_MASK_ALL);

/* Timeout control disable */
GPMCTimeoutEnable(pGpmcinit->gpmcBaseAddr, FALSE);

GPMCChipSelEnable(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,FALSE);

/*Set device type as NOR*/
GPMCSetDevType(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,GPMC_DEV_TYPE_NOR);
/*Set device size as 16 bit*/
GPMCSetDevSize(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,GPMC_DEV_SIZE_16BIT);
/*Set as Address and Data Multiplexed device.*/
GPMCSetAddrDataMuxType(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,GPMC_MUX_TYPE_ADDR_DATA);
/*Disable Interrupt*/
GPMCIntrDisable(pGpmcinit->gpmcBaseAddr,GPMC_INTR_MASK_ALL);

GPMCSetTimeParaGranularity (pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,GPMC_TIME_GRANULARITY_X1);
GPMCSetFclkDivider(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,GPMC_FCLK_DIVIDER_2); //fclk/2
GPMCSetClkActivationTime(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,0x01);

/* set single read and single write mode */
GPMCSetAccessType(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,GPMC_ACCESS_TYPE_SYNC_READ);
GPMCSetAccessType(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,GPMC_ACCESS_TYPE_SYNC_WRITE);
GPMCSetAccessMode(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,GPMC_OPER_MODE_READ,GPMC_ACCESS_MODE_SINGLE);
GPMCSetAccessMode(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,GPMC_OPER_MODE_WRITE,GPMC_ACCESS_MODE_SINGLE);

/* base address and mask address */
/*32 Mb */
GPMCSetChipSelBaseAddr(pGpmcinit->gpmcBaseAddr, pGpmcinit->csNum, 0x01);
GPMCSetChipSelMaskAddr(pGpmcinit->gpmcBaseAddr, pGpmcinit->csNum, GPMC_CS_SIZE_32MB);

/* FPGA timings configuration */
GPMCChipSelectTimingConfig(pGpmcinit->gpmcBaseAddr, pGpmcinit->csNum,&fpga_cs);
GPMCAdvSignalTimingConfig(pGpmcinit->gpmcBaseAddr, pGpmcinit->csNum,&fpga_adv);
GPMCWeOeSignalTimingConfig(pGpmcinit->gpmcBaseAddr, pGpmcinit->csNum,&fpga_oe);
GPMCReadAccessTimingConfig(pGpmcinit->gpmcBaseAddr, pGpmcinit->csNum,&fpga_rd);
GPMCCycleDelayTimingConfig(pGpmcinit->gpmcBaseAddr, pGpmcinit->csNum,&fpga_cycle);
GPMCWriteAccessTimingConfig(pGpmcinit->gpmcBaseAddr, pGpmcinit->csNum,FPGA_WRACCESSTIME,FPGA_WRDATAONADMUXBUS);

/* Wait pin Configuration */
GPMCWaitPinMonitoringEnable(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,GPMC_OPER_MODE_READ,GPMC_WAIT_PIN_MONITOR_DISABLE);
GPMCWaitPinMonitoringEnable(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,GPMC_OPER_MODE_WRITE,GPMC_WAIT_PIN_MONITOR_DISABLE);

/* Enable Chip select */

GPMCChipSelEnable(pGpmcinit->gpmcBaseAddr,pGpmcinit->csNum,TRUE);

value= ((*(volatile unsigned short *)(0x00100000)));

return status;
}