Mapping DDR3 datalines with AM3352

Ashika Ashok11

Other Parts Discussed in Thread: AM3352

We are working on the AM3352 interface with DDR3 part number MT41J256M16HA-125

We have a query related to interfacing the DDR data lines with AM3352.

In the datasheet of AM3352 (pg 172) direct pin mapping is done between the datelines of AM3352 DDR_D[0: D15] to DQ[0:15]

We referred the 2 reference designs

1. am335x_gpevm_zczbaseboard_3h0002_schematic_rev1_6a (page 7/16)

In this reference direct mapping is done as seen in datasheet

2. TMDSSK3358_1.2A (page 7/17)

In 2nd reference they have mapped the data lines of AM3352 as DDR_D3 with DQ0 of DDR3 which is not direct mapping.

We wanted to know the correct mapping of datalines with DDR3 using AM3352 . Kindly help us in this issue

Thank you

Ashika

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi Ashika,

If you check carefully you will see that data bits are swapped within the byte boundary. To say this differently - you may swap bits within the byte lane to facilitate PCB routing. Additionally each byte lane must have the corresponding DM/DQS/DQSn signals routed correspondingly. Bit swapping is absolutely prohibited across bytes. Also the Address, Clock and Control signals must never be swapped.