OMAPL138 McBSP CLKGDV setting

Hi,

Thanks for your post.

In general, bit clock frequency should be equal to the McBSP clock.

                         Clock Frequency = McBSP Internal Clock / (CLKGDV + 1)         //CLKGDV  = 0 as per the settings

and SRGR register 0x01d11014 - 201f0000  // 00 - CLKGDV.

Try increasing the CLKGDV value. Even, CLKGDV value of 1 should work fine.

Thanks & regards,

Sivaraj K

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Hi Sivaraj,

Thanks for the reply.

Are you saying that a CLKGDV of zero should be okay?

Is the internal clock (SCLKME, CLKSM = 0, 1) used for anything else inside the McBSP module before it is divided down? This statement in SPRS586I:

'If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater.'

implies that the clock must be getting used for something else before it is divided down otherwise why would it matter. Is the non-divided clock used to drive other parts of the McBSP block?

What we are seeing is that when CLKGDV is zero there is a reliability problem, if we change the PLL settings so we have to use CLKGDV = 1 to use the same McBSP frequency this reliability problem goes away.

We would like to understand exactly what the limitation is so we can work out if we can workaround it some how.

Thanks

Nigel

Hi,

We've now been running with a non-zero CLKGDIV in the McBSP config and it appears to be stable. 

This does seem to show that the PLL clock has to be greater than the data clock by some amount, would be good for this relationship to be mentioned in the documentation somewhere (or if it already is make it more obvious).

Thanks

Nigel