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Pulse at GIO at startup

Par-Ola Svensson
Prodigy 20 points

When we power up the system we control all power supplies and holds the reset signal low until all rails are up.

GPIO60 is used to reset our power hold circuit  (shut down the system). The problem is that GPIO60 is making a short positive pulse (nice and square 3,3V pulse with approx 7us duration). It is happening when the reset signal reaches approx 2V. This pulse resets the power hold circuit and shuts the system down again.

Why do I get that pulse on the GPIO60 during power up? Is there some way to avoid it except low pass filtering outside DM365.

 

/Par-Ola

  • 0
    Guru 227245 points

    After a reset, usually all port pins are configured as I/O input. Depending on the device, they are either high-impedance or have an internal pullup active. This is interpreted as high by most circuitry.

    If you want the signal to stay low across a reset and only high if you program it through I/O, you'll need to attach a pulldown resistor to the pin that holds the signal low until the application software switches the I/O pin to low output. Also, first program the PxOUT register, then the PxDIR register, so you're not driving the pin actively high after setting it to output, until it is set low a few clock cycles later. (the register names are from the MSP series, but I guess the  DM works similar in this aspect)

  • 0 in reply to Jens-Michael Gross
    Prodigy 20 points

    This GIO has it's default setting as input, and i do have a 10k pulldown on the pin. Thats why I'm very surprised of this bahaviour. I have this bahaviour also when starting the DM365 with NAND boot setting, connected to an empty NAND. The puls comes close to the time when the reset pin reaches 2V (I/O high level value). Can this behaviour be related to some dafault register state setting in the DM365?

  • 0 in reply to Par-Ola Svensson
    Guru 227245 points

    I'm not familiar with the Arm9 based DM3 family, but a look in to the datasheet reveals that "RESET must be low until all supplies are ramped up".

    If your reset line follows the rising supply voltages too fast, the core will be released from reset state before the I/O supply has ramped up properly, resulting in erraneous port behaviour. You should add a capacitor (or increase the existing one) to the RESET line or increase the pullup resistor that pulls the line high. (depending on your reset logic).

    Decreasing your 10k pulldown to 4,7k might help too as a quickhack (I don't know what's going wrong in the port logic when the I/O coltage hasn't stabilized)

  • 0 in reply to Par-Ola Svensson
    TI__Genius 9490 points

    Par-Ola,

    What is the Value of the AECFG[2] pin at reset?  Depending on the AECFG2 (EM_A10/GIO75/AECFG[2] pin name) pin setting. the EM_D[15:0] or EM_D[7:0] are selected else the GIO60/EM_D11/HD11 pin defaults to a GPIO and is set to be an input by default and can be getting driven externally by something in your system.

    Also, what boot mode is your system supposed to be using? since you mentioned that you 'also see the behavior when selecting NAND boot setting.

    BTSEL[2:0] AND AECFG[2:0] pins are latched at reset and depending on their state the specific boot mode and AEMIF Data and Address pins are set regardless of the PINMUX register settings.

    This is some information to help you with the debug, from the SW or register perspective.  But I totally agree with Jens-Michael Gross on the HW recommendations.

    regards,

    miguel