HI dear ,I'm sorry that my English is very poor.
Our products use the C6747, run the program which load from FLASH to the SDRAM . Found a lot of board can not run the program affter two years later .We compared the difference between the new and the damaged circuit board .Found that the amplitude of the SDRAM's clock has changed,like list picture
Damaged board clk ok board CLK
Here is our circuit diagram
Here is our EMB configuration with the SDRAM connection
void InitPLL1(void)
{
int i = 0;
/* Configure ARM, DSP at 300MHz, EMIFs at 133MHz */
//Uint8 DIV45_EN = 1;
Uint8 CLKMODE = 0;
Uint8 PLLM = 29;
//Uint8 PLLM = 14;//150M
Uint8 POSTDIV = 1;
Uint8 PLLDIV3 = 2;
Uint8 PLLDIV5 = 3;
Uint8 PLLDIV7 = 7;
Uint8 PREDIV = 0;
// Moved step 2c and 2d to step 0
/*Set PLLEN=0 and PLLRST=0, Reset the PLL*/
PLL0_PLLCTL &= 0xFFFFFFFE; /*PLL BYPASS MODE*/
/*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
for(i=0; i<PLLEN_MUX_SWITCH; i++) {;} /*Make PLLEN_MUX_SWITCH as bootpacket*/
/*Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
PLL0_PLLCTL &= 0xFFFFFEFF;
PLL0_PLLCTL |= (CLKMODE<<8); /* Make CLKSRC as BootPacket to pass the value*/
/*Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR*/
PLL0_PLLCTL &= 0xFFFFFFDF;
/*PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Primus*/
PLL0_PLLCTL &= 0xFFFFFDFF;
/* Clear PLLRST bit to 0 -Reset the PLL */
PLL0_PLLCTL &= 0xFFFFFFF7;
/*Disable the PLL output*/
PLL0_PLLCTL |= 0x10;
/*PLL initialization sequence*/
/*Power up the PLL- PWRDN bit set to 0 to bring the PLL out of power down bit*/
PLL0_PLLCTL &= 0xFFFFFFFD;
/*Enable the PLL from Disable Mode PLLDIS bit to 0 - This is step is not required for Primus*/
PLL0_PLLCTL &= 0xFFFFFFEF;
/*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
// for(i=0; i<PLL_STABILIZATION_TIME; i++) {;} /* Make PLL_STABILIZATION_TIME as bootpacket*/
PLL0_PREDIV = 0x8000 | PREDIV;
/*Program the required multiplier value in PLLM*/
PLL0_PLLM = PLLM; /* Make PLLMULTIPLEIR as bootpacket*/
/*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
PLL0_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/
/*If Necessary program the PLLDIVx*/
/*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
while(PLL0_PLLSTAT & 0x1==1){}
/*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
PLL0_PLLDIV3 = 0x8000 | PLLDIV3; /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/
PLL0_PLLDIV5 = 0x8000 | PLLDIV5; /* Make PLLDIV5 as bootpacket, do it for other PLLDIVx to if required*/
PLL0_PLLDIV7 = 0x8000 | PLLDIV7; /* Make PLLDIV7 as bootpacket, do it for other PLLDIVx to if required*/
/*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
PLL0_PLLCMD |= 0x1;
/*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
while(PLL0_PLLSTAT & 0x1==1) { }
/*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
// for(i=0; i<PLL_RESET_TIME_CNT; i++) {;} /*128 MXI Cycles*/ /*Make PLL_RESET_TIME_CNT as boot packet*/
/*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
PLL0_PLLCTL |= 0x8;
/*Wait for PLL to lock. See PLL spec for PLL lock time*/
for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/
/*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
PLL0_PLLCTL |= 0x1;
KICK0R = 0x83e70b13; // Kick0 register + data (unlock)
KICK1R = 0x95a4f1e0; // Kick1 register + data (unlock)
CFGCHIP3 |= 0x4; // Enable 4.5 divider PLL
CFGCHIP3 &= 0xfe;
//CFGCHIP3 |= 0x1; // Select 4.5 divider for EMIFB clock source only (not EMIFA)
}
void emifconfig1(void)
{
// ISSI IS42S16160B-6BL SDRAM, 2 x 16M x 16 (32-bit data path), 133MHz
EMIFB_SDCFG = 0 // SDRAM Bank Config Register
|( 1 << 15) // Unlock timing registers
|( 3 << 9 ) // CAS latency is 3
|( 2 << 4 ) // 4 bank SDRAM devices
|( 1 << 0 ); // 512-word pages requiring 9 column address bits
EMIFB_SDREF = 0 // SDRAM Refresh Control Register
|( 0 << 31) // Low power mode disabled
|( 0 << 30) // MCLK stoping disabled
|( 0 << 23) // Selects self refresh instead of power down
|(1038 <<0);
EMIFB_SDTIM1 = 0 // SDRAM Timing Register 1
|( 8<< 25) // (67.5ns / 7.55ns) - 1 = TRFC @ 133MHz 70ns
|( 2 << 22 ) // (20ns / 7.5ns) - 1 =TRP 20ns
|( 2 << 19 ) // (20ns / 7.5ns) - 1 = TRCD 20ns
|( 1 << 16 ) // (14ns / 7.5ns) - 1 = TWR 20ns
|( 5 << 11 ) // (45ns / 7.5ns) - 1 = TRAS 50ns
|( 8 << 6 ) // (67.5ns / 7.5ns) - 1 = TRC 70ns
|( 1 << 3 ); // *(((4 * 14ns) + (2 * 7.5ns)) / (4 * 7.5ns)) -1. = TRRD
// but it says to use this formula if 8 banks but only 4 are used here.
// and SDCFG1 register only suports upto 4 banks.
EMIFB_SDTIM2 = 0 // SDRAM Timing Register 2
|( 13<< 27) //2015.3.24 16 改为13 // not sure how they got this number. the datasheet says value should be
// "Maximum number of refresh_rate intervals from Activate to Precharge command"
// but has no equation. TRASMAX is 120k.
|( 9 << 16) // ( 70 / 7.5) - 1 70ns
|( 5 << 0 ); // ( 45 / 7.5 ) - 1 40ns
EMIFB_SDCFG = 0 // SDRAM Bank Config Register
|( 1 << 16)
|( 0 << 15) // Unlock timing registers
|( 3 << 9 ) // CAS latency is 2
|( 2 << 4 ) // 4 bank SDRAM devices
|( 1 << 0 ); // 512-word pages requiring 9 column address bits
}
Now we use the DSP frequency of 600MHz, SDRAM frequency of 133Mhz
There is a strange phenomenon, if I use the electric iron heating C6747, the program can run normally. When it cooling, I power on the board it can not run again. If I reduce the frequency of SDRAM, the program can run normally too.
I modify the configuration, so that the program is loaded into the internal RAM of DSP, and check the external SDRAM by reading and writing data. The result is all pass.
So We want to consult what is wrong with the DSP ?
We have done a lot of experiments, such as HALT & HASS, Vibration Test, low high temperature test .
please help us,thank you very much.
