This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

OMAPL138 PLL Initializaiton Procedure

Other Parts Discussed in Thread: OMAPL138, OMAP-L138

Hi,

I have a question about OMAPL138 PLL initializaiton procedure.

I refer to device_PLL0() in EVMOMAPL138_ARM.gel included in CCSv6.
In device_PLL0(), there are the following code.

   /* Set PLLEN=0 to put in bypass mode*/
   PLL0_PLLCTL &= ~(0x00000001);

   /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
   for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

   ....

   /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
   for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

Is this waiting time(PLL stabilisation time) necessary in here?
If comment is correct, I think that it is not necessary, because PLL is in bypass mode already at that point.

I checked OMAPL138 Technical Reference Manual and datasheet, but was not able to find the description about it.
Please tell me whether waiting time(PLL stabilisation time) is necessary or not, in OMAPL138 PLL initialization procedure.

Best Regards,
Yasunori

  • Hi,

    We are working on this request and will get back to you at the earliest.

    Thanks & regards,
    Sivaraj K
  • Hi Yasunori,

    In EVMOMAPL138_ARM.gel file, the code for stabilization is generic for the three PLL sequence mentioned in the OMAPl138 TRM.

    Actually, after power up and the frequency lock sequence of PLL is complete, the PLL will be ready for any configuration modes ( i.e. PLLM or bypass mode ). 

    1. Consider if the PLL0 is already intialized and configured in bypass mode, then the code below for stabilization is not required. But if the PLL0 is already in PLLM mode, then it might be required for transition and stabilization. And more over, for your project requirement, if the change sequence of PLL is wellknown and fixed ,then you can either remove or modify by reducing the stabilisation time.

    /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/

      for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

    When we compared to the gel file of OMAPL137, as it has only one function, Setup_PLL(), this stabilization waitcycles code is commented out. There is no separate functions like Set_Core_456MHz(), Set_Core_300MHz().

     

     

     

     

  • Hi Shankari,

    Thank you for your reply.
    I understand that "stabilization time" is not required if PLL is already configured in bypass mode.

    I have additional questions. Please tell me the following.

    1 .
    The three PLL sequence, I think the following three.
    OMAP-L138 TRM (spruh77a.pdf)
    - 8.2.2.2 Initializing PLL Mode from PLL Power Down
    - 8.2.2.3 Changing PLL Multiplier
    - 8.2.2.4 Changing SYSCLK Dividers

    "8.2.2.2" and "8.2.2.3", I think "stabilization time" is not required because they contains "Switch the PLL to bypass mode" (PLL is configured in bypass mode).
    "8.2.2.4" does not contain "Switch the PLL to bypass mode", but, "stabilization time" is not included in the corresponding part in device_PLL0().
    ---------------------------------------------
    /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
    while(PLL0_PLLSTAT & 0x1==1){}

    /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
    PLL0_PLLDIV1 = 0x8000 | PLLDIV1; /* Make PLLDIV1 as bootpacket, do it for other PLLDIVx to if required*/
    PLL0_PLLDIV2 = 0x8000 | PLLDIV2;
    PLL0_PLLDIV4 = 0x8000 | (((PLLDIV1+1)*4)-1);
    PLL0_PLLDIV6 = 0x8000 | PLLDIV1;
    PLL0_PLLDIV3 = 0x8000 | PLLDIV3; /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/
    PLL0_PLLDIV7 = 0x8000 | PLLDIV7; /* Make PLLDIV7 as bootpacket, do it for other PLLDIVx to if required*/


    /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
    PLL0_PLLCMD |= 0x1;

    /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
    while(PLL0_PLLSTAT & 0x1==1) { }
    ---------------------------------------------

    Also, in clock.c contained in the OMAPL138 PSP (linux-xxxx/arch/arm/mach-davinci/clock.c), it does not found.
    - davinci_set_pllrate(): for "8.2.2.3 Changing PLL Multiplier"
    - davinci_set_sysclk_rate(): for "8.2.2.4 Changing SYSCLK Dividers"
    In either case, "stabilization time" does not found.

    so, I think "stabilization time" is not required in the three(all) PLL sequence.
    Is this correct ?

    2.
    If there is a case that "stabilization time" is required,
    what kind of case is it ?
    how long time is needed ?

    Best Regards,
    Yasunori
  • Hi Yasunori,

    Yes, in TRM, there is no mention about the stabilization time. But when migrating the gel file from OMAPL137 to OMAPL138, they enabled that code.

    case 2:

    Yasunori said:
     If there is a case that "stabilization time" is required,

    what kind of case is it ?

    how long time is needed ?

    Thinking of cases like changing the core frequency using CCS gel script options. For example:- From Set_Core_300MHz to Set_Core_456MHz().

    To conclude this firmly, that this stablization time is not required, my suggestion is, please remove the stabilization code in gel file and change the core frequency using the CCS script option of gel file and check that the effect is NIL.

    Run by changing the core frequency multiple times.

    Regards,

    Shankari

  • Hi Shankari,

    Thank you for your reply.
    I understood that "stabilization time" is not required in the three PLL sequence.

    > For example:- From Set_Core_300MHz to Set_Core_456MHz().

    Both Set_Core_300MHz() and Set_Core_456MHz() calls device_PLL0().
    In device_PLL0(), PLL is put in bypass mode. (before to program)
    Therefore, I think that "stabilization time" is not required in this case.

    Best Regards,
    Yasunori
  • Hi Yasunori,

    As per the code flow, thats my understanding too.

    But by any chance you experimented?? to confirm it??

  • Hi Shankari,

    > please remove the stabilization code in gel file and change the core frequency
    > using the CCS script option of gel file and check that the effect is NIL.
    >
    > Run by changing the core frequency multiple times.

    I confirmed it using OMAP-L138 LCDK + gel (removed the stabilization code),
    but, no problem has occurred. The PLL registers has been changed as expected.

    Additionally, I confirmed it using OMAP-L138 LCDK + starterware.
    Using a timer example(timerCounter.c), I modified it to change the core frequency multiple times after timer interrupt has occurred.
    This worked normally, too. (no problem has occurred.)

    After all, I think that "stabilization time" is not required.

    Best Regards,
    Yasunori
  • Hi Yasunori,

    Superb job.

    Thanks for your effort in confirming this. This information will be useful for the community members.
    On your post above, please click on verify answer button.

    In the next release ( if any ) , I would like to bring your observation to the internal team to remove the stabilization code in the gel file.

    Thanks.