Hi,
I have a question about OMAPL138 PLL initializaiton procedure.
I refer to device_PLL0() in EVMOMAPL138_ARM.gel included in CCSv6.
In device_PLL0(), there are the following code.
/* Set PLLEN=0 to put in bypass mode*/
PLL0_PLLCTL &= ~(0x00000001);
/*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}
....
/*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}
Is this waiting time(PLL stabilisation time) necessary in here?
If comment is correct, I think that it is not necessary, because PLL is in bypass mode already at that point.
I checked OMAPL138 Technical Reference Manual and datasheet, but was not able to find the description about it.
Please tell me whether waiting time(PLL stabilisation time) is necessary or not, in OMAPL138 PLL initialization procedure.
Best Regards,
Yasunori