This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

am335x ADPLLS formulas

In the TRM, Table 8-17 shows the formula for CLKDCOLDO = 2 * [M / (N + 1)] * CLKINP. However, in the diagram (Figure 8-8), I can not find out where the (x2) comes from. The x2 is also why for CLKOUT, we don't divide by 2 as Figure 8-8 shows happening before CLKOUT enters the mux. It is really just for informational purposes, but it would be great to know where the x2 comes from.

Thanks.

David

  • Here's a markup showing where it comes from:

    Note that since this "1/2" is in the feedback path of the PLL, it has the end effect of making the resulting frequency twice as fast.  The 1/M2 and and 1/2 following it are NOT in the feedback path and so those are functioning as frequency dividers.