tms3205515 I2C slave interrupt example (CSL or resgisters)

After few minutes reading datasheet sprufo1a.pdf :
2.11.2 Configuring the I2C in Slave Receiver and Transmitter Mode
The following initialization procedure is for the I2C controller configured in Slave Receiver and Transmitter
mode.
1. Enable I2C clock from PSC Level. Do this so that you will be able to configure the I2C registers.
2. Place I2C in Reset (Clear IRS bit).
• ICMDR.IRS=0.
3. Assign the Address (7-bit or 10-bit address) to which the I2C Controller will be responding. This is the
Address that the Master is going to broadcast when attempting to start communication with this slave
device; I2C Controller.
• If the I2C is able to respond to 7-bit Addressing: Configure ICMDR.XA=0.
• If the I2C is able to respond to 10-bit Addressing: Configure ICMDR.XA=1.
• Program ICOAR=Assigned Address (7-bit or 10-bit address).
4. Enable the desired interrupt you need to receive by setting the desired interrupt bit field within ICIMR to
enable the particular Interrupt.
• ICIMR.AAS=1; Expect an interrupt when Master's Address matches yours (ICOAR programmed
value).
• ICIMR.ICRRDY=1; Expect a receive interrupt when a byte worth data sent from the master is
ready to be read.
• ICIMR.ICXRDY=1; Expect to receive interrupt when the transmit register is ready to be written with
a new data that is to be sent to the master.
• ICIMR.SCD=1; Expect to receive interrupt when Stop Condition is detected.
5. Configure the I2C Controller Operating frequency; this is not the serial clock frequency. This should be
between 6.7 and 13.3 MHz. Program IPSC to generate a 6.7 to 13.3 MHz operating frequency.
• Prescaled Module Clock Frequency = PLL1 Output Frequency / (IPSC + 1).
6. Configure the I2C Serial Clock Frequency. It is advised to configure this frequency to operate at 400
KHz. This will allow the slave device to be able to attend to all Master speeds. Program ICCH and
ICCL.
• 400 KHz = I2C Operating Frequency (6.7-13.3 MHz from Step 5) / [(ICCH+5) + (ICCL+5)].
• If ICCL==ICCH ≥ 400 KHz = Prescaled Module Clock Frequency / [2×ICCH+10].
7. Configure the Mode Register.
• ICMDR.MST=0; Configure the I2C Controller to operate as SLAVE.
• ICMDR.FDF=0; Free Data Format is disabled.
• ICMDR.BC=0; Set data width to 8 bytes.
• ICMDR.DLB=0; Disable Loopback Mode.
• ICMDR.STB=0; I2C Controller can detect Start condition via H/W.
• ICMDR.RM=1, STP=0, STT=1. See Table 16. (No Activity case).
• Configure remaining bits other than ICMDR.IRS to 0.
8. Release I2C from Reset.
• ICMDR.IRS=1; Make sure you do not over write your previous configurations.
9. Make sure Interrupt Status Register is cleared.
• ICSTR=ICSTR; Clear Interrupt fields that require writing '1' requirements.
• While (ICIVR != 0) Read ICIVR; Read until it is cleared to Zero.
20 Inter-Integrated Circuit (I2C) Peripheral SPRUFO1A–September 2009
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
www.ti.com Peripheral Architecture
10. Instruct I2C Controller to detect START Condition and Its Own Address.
• ICMDR.STT=1; Make sure you do not over write your previous configurations.
MASTER desires to perform a write transfer.
11. If Master requests a Write, i.e, I2C needs to receive data, perform the following:
• Wait for Receive Interrupt to be received, i.e, ICSTR.ICRRDY=1.
• Read Data.
12. Perform Step 11 until one of the two happens:
• Master generates a STOP Condition (ICSTR.STP=1) or
• I2C Slave desires to end receive transfer.
If the latter, then the I2C needs to Not Acknowledge the last byte to be received from the Master.
After reading the byte prior from the last byte, set NACKMOD bit so that the I2C automatically
NACKs the following received data byte, which is the last data byte.
• ICMDR.NACKMOD=1; set this field on the 2nd data prior from the last.
Master desires to perform a read transfer.
13. If Master requests a Read, i.e, I2C needs to transmit data, perform the following.
• Write Data.
• Wait for Transmit Interrupt to be received, i.e, ICSTR.ICXRDY=1.
14. Perform step 13 until a STOP condition is detected, i.e. (ICSTR.STP=1).
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Code initiliazation :
-----------------------------
/* Configure I2C for salve recievr mode and enable loopback mode */
i2cConfig.icoar = 0x48;
i2cConfig.icimr = 0xFF;
i2cConfig.icclkl = CSL_I2C_ICCLK_DEFVAL;
i2cConfig.icclkh = CSL_I2C_ICCLK_DEFVAL;
i2cConfig.iccnt = 0;

//i2cConfig.icsar = CSL_I2C_ICSAR_DEFVAL; Slave address
i2cConfig.icsar = 0x48;
//i2cConfig.icsar = 0x55;
//i2cConfig.icmdr = (CSL_I2C_ICMDR_WRITE_DEFVAL | CSL_I2C_ICMDR_DLB_MASK); //DLB is loopback
i2cConfig.icmdr = 0x2080;//RM + STT 0x2080 STT
i2cConfig.icmdr |= 0x0020; //Enable I2C

i2cConfig.icemdr = CSL_I2C_ICEMDR_DEFVAL;
i2cConfig.icpsc = CSL_I2C_ICPSC_DEFVAL;

status = I2C_config(&i2cConfig);
if(status != CSL_SOK)
{
printf("I2C Config Failed!!\n");
return(result);
}
CSL_I2C_SETSTART();
while (1)
{
// CSL_I2C_SETSTOP();
/* Set the start bit */

/* Read the data from I2C data receive register */
CSL_I2C0_READREG(ICSTR, InterruptsVal);
//CSL_I2C_ICIMR_ICRRDY_MASK

if (InterruptsVal&0x0C)
InterruptCounter++;
}


I will update when I have more updates.

Hi,

Your approach seems to be correct. let us know if you need further information on this..

Regards

 Vasanth

Hi Vasanth ,

It would be great if you can supply I2C slave interrupt driver.

Thank you,
Eli