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AM57xx ECC

Michi Yama
Guru 10030 points

Hi,

I would like to know the behaviour of AM57xx with ECC enable.

Please see the below results. These are results of reading DDR data. DDR3 memory is not cleared before access with ECC enabled.

1. When ECC is enalbed, the address of ECC protected region is read "00000000" out. (Default case in the below)

2. When ECC is enalbed, the data is written in DDR memory. But the read out data is "00000000" until 16byte(128bit) is written.

Default

   ECC ON  00000000 00000000 00000000 00000000

   ECC OFF FFFBFFFF FF7FFFFF FFFFFFFF FFFFFFFF

 

  Address 0x0: 0x11111111 WRITE

   ECC ON  00000000 00000000 00000000 00000000

   ECC OFF 11111111 FF7FFFFF FFFFFFFF FFFFFFFF

 

Address : 0x4 :0x22222222 WRITE

   ECC ON  00000000 00000000 00000000 00000000

   ECC OFF 11111111 22222222 FFFFFFFF FFFFFFFF

 

Address : 0x8 :0x33333333 WRITE

   ECC ON  00000000 00000000 00000000 00000000

   ECC OFF 11111111 22222222 33333333 FFFFFFFF

 

Address 0xC :0x44444444 WRITE

   ECC ON  11111111 22222222 33333333 44444444

   ECC OFF 11111111 22222222 33333333 44444444

Is this correct behavior?

Please advise me.

Best regards,

Michi

  • 0
    TI__Guru**** 393215 points
    Hi,

    I will ask the DDR experts.
  • 0
    TI__Guru*** 125430 points

    Michi Yama said:
    DDR3 memory is not cleared before access with ECC enabled.

    You are required to initialize all the data with quanta sized and quanta aligned writes immediately after enabling the ECC.

  • 0 in reply to Brad Griffis
    Guru 10030 points

    Dear Brad-san,

    Thank you for your quick reply.

    I would like to reconfirm your answer.

    > You are required to initialize all the data with quanta sized and quanta aligned writes immediately after enabling the ECC.

    Does this mean that All ECC protected area must be written with some data (ex. all 0x0000, all 0xFFFF etc) once after enabling the ECC?

     If the above initialization does not execute, the read out data from ECC protected area is "0000" as my customer experienced?

    Please advise again.

    I appreciate your quick reply.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    TI__Guru*** 125430 points

    Michi Yama said:

    > You are required to initialize all the data with quanta sized and quanta aligned writes immediately after enabling the ECC.

    Does this mean that All ECC protected area must be written with some data (ex. all 0x0000, all 0xFFFF etc) once after enabling the ECC?

    Yes.  That shouldn't be a surprise.  Here's a quote from the TRM:

    • "Once ECC is enabled the entire protected region must be initialized with data. These writes must be quanta-sized and quanta-aligned."

    Michi Yama said:

     If the above initialization does not execute, the read out data from ECC protected area is "0000" as my customer experienced?

    It's not surprising for uninitialized (discharged) DRAM to read back as zero.  I would expect to see ECC errors in the case you're reading back uninitialized data.

  • 0 in reply to Brad Griffis
    Guru 10030 points
    Dear Brad-san,

    Thank you for your quick reply.

    The below is my understaing.

    * In my customer's case, the initialization was not executed. This means that read back data may be "zero" because of no charge. to DDR
    memory. And the important thing is "ECC error" is triggered.

    * When the initialization, the writes must be quanta-sized(32bit size). 128bit(16bytes) size is not needed for intialization.

    Is the above my understanding right?


    Best regards,
    Michi
  • 0
    Guru 10030 points

    Hi,

     

    I would like to confirm the behavior of some registers relative ECC function when ECC error happened. Please see the below my question.

     

    1) EMIF1_EMIF_1B_ECC_ERR_CNT register : Does this register increase 4 counts every 1-bit error occurrence?

    2) EMIF1_EMIF_1B_ECC_ERR_DIST_1 register :  the bit of register that 1-bit error happened is set. Writing 1 to this register clears  bits of the register. If this register is not cleared, register is overlayed. Is my understanding right?

    3) EMIF1_EMIF_1B_ECC_ERR_ADDR_LOG register  :  Are four lsb bits(3 bit - 0 bit) of this register always "zero" ?

    4) EMIF1_EMIF_1B_ECC_ERR_ADDR_LOG register : This register is FIFO, and four address is stored. But the data of same addresses are stored in this FIFO. Is it right behavior?

    5) When 2B_ECC_ERR happened, 128 bit "0" data is read out from this error address. Is this beavior right?

     

     

    The above question is from my customer's test results. Please show the below test.

     

     

    * Confirmation results of ECC 1B error :

    Procedure and results

     

    1．ECC Enable

    EMIF1_EMIF_ECC_CTRL_REG                             C0000003

    EMIF1_EMIF_ECC_ADDRESS_RANGE_1           00000000  <- 0x80000000 – 0x8000FFFF

    EMIF1_EMIF_ECC_ADDRESS_RANGE_2           00010001  <- 0x80010000 – 0x8001FFFF

     

    2．Memory Initialization

           Address 0x80000000 – 0x8001FFFF  are clread by Fill command

     

    3．test data setting

    0x80000000   00000001      00000002      00000004      00000008

    0x80000010   00000010      00000020      00000040      00000080

    0x80000020   00000100      00000200      00000400      00000800

    0x80000030   00001000      00002000      00004000      00008000

    0x80000040   00010000      00020000      00040000      00080000

    0x80000050   00100000      00200000      00400000      00800000

    0x80000060   01000000      02000000      04000000      08000000

    0x80000070   10000000      20000000      40000000      80000000

     

    4 ．ECC Disable

    EMIF1_EMIF_ECC_CTRL_REG                   00000000

     

    5. Bit change @0x80000078 for making ECC 1bit error

    0x80000000   00000001      00000002      00000004      00000008

    0x80000010   00000010      00000020      00000040      00000080

    0x80000020   00000100      00000200      00000400      00000800

    0x80000030   00001000      00002000      00004000      00008000

    0x80000040   00010000      00020000      00040000      00080000

    0x80000050   00100000      00200000      00400000      00800000

    0x80000060   01000000      02000000      04000000      08000000

    0x80000070   10000000      20000000      00000000      80000000

     

    6．ECC Enable

    EMIF1_EMIF_ECC_CTRL_REG                   C0000003

     

    7．Confirmed ECC 1Bit correction

    0x80000000   00000001      00000002      00000004      00000008

    0x80000010   00000010      00000020      00000040      00000080

    0x80000020   00000100      00000200      00000400      00000800

    0x80000030   00001000      00002000      00004000      00008000

    0x80000040   00010000      00020000      00040000      00080000

    0x80000050   00100000      00200000      00400000      00800000

    0x80000060   01000000      02000000      04000000      08000000

    0x80000070   10000000      20000000     40000000       80000000

     

     

    8．Check the status

    EMIF1_EMIF_ECC_CTRL_REG                                   C0000003

    EMIF1_EMIF_ECC_ADDRESS_RANGE_1                  00010000

    EMIF1_EMIF_ECC_ADDRESS_RANGE_2                   00020001

    EMIF1_EMIF_READ_WRITE_EXECUTION_THRESHOLD 00000305

    EMIF1_EMIF_COS_CONFIG                                         00FFFFFF

    EMIF1_EMIF_1B_ECC_ERR_CNT                 　　　　     00000004      (Error count is four)

    EMIF1_EMIF_1B_ECC_ERR_THRSH               　　　　  00000000

    EMIF1_EMIF_1B_ECC_ERR_DIST_1                     　   40000000      (error bit is showed)

    EMIF1_EMIF_1B_ECC_ERR_ADDR_LOG               　 0000070  (Error happened at 0x80000000 + 0x00000070 = 0x8000007X.)

    EMIF1_EMIF_2B_ECC_ERR_ADDR_LOG                   00000000

     

    9．Repeat 4 - 8 Bit change @0x80000064 for making ECC 1bit error

    0x80000000   00000001      00000002      00000004      00000008

    0x80000010   00000010      00000020      00000040      00000080

    0x80000020   00000100      00000200      00000400      00000800

    0x80000030   00001000      00002000      00004000      00008000

    0x80000040   00010000      00020000      00040000      00080000

    0x80000050   00100000      00200000      00400000      00800000

    0x80000060   01000000     00000000     04000000      08000000

    0x80000070   10000000      20000000     00000000     80000000

     

    EMIF1_EMIF_ECC_CTRL_REG                        　C0000003

    EMIF1_EMIF_ECC_ADDRESS_RANGE_1                   00010000

    EMIF1_EMIF_ECC_ADDRESS_RANGE_2                   00020001

    EMIF1_EMIF_READ_WRITE_EXECUTION_THRESHOLD 　00000305

    EMIF1_EMIF_COS_CONFIG                           　00FFFFFF

    EMIF1_EMIF_1B_ECC_ERR_CNT                 　　　　0000000C      (Error count is "0xC" ( 4(for first error) + 4*2 (for second error) = 12 ))

    EMIF1_EMIF_1B_ECC_ERR_THRSH               　　　　00000000

    EMIF1_EMIF_1B_ECC_ERR_DIST_1                     　42000000      (error bit is overlayed)

    EMIF1_EMIF_1B_ECC_ERR_ADDR_LOG                   00000070

    EMIF1_EMIF_2B_ECC_ERR_ADDR_LOG                   00000000

     

    9．Repeat 4 - 8 Bit change @0x80000040　

    0x80000000   00000001      00000002      00000004      00000008

    0x80000010   00000010      00000020      00000040      00000080

    0x80000020   00000100      00000200      00000400      00000800

    0x80000030   00001000      00002000      00004000      00008000

    0x80000040   00000000      00020000      00040000      00080000

    0x80000050   00100000      00200000      00400000      00800000

    0x80000060   01000000     00000000     04000000      08000000

    0x80000070   10000000      20000000     00000000     80000000

     

    EMIF1_EMIF_ECC_CTRL_REG                         　C0000003

    EMIF1_EMIF_ECC_ADDRESS_RANGE_1                   00010000

    EMIF1_EMIF_ECC_ADDRESS_RANGE_2                   00020001

    EMIF1_EMIF_READ_WRITE_EXECUTION_THRESHOLD 　00000305

    EMIF1_EMIF_COS_CONFIG                          　　00FFFFFF

    EMIF1_EMIF_1B_ECC_ERR_CNT                 　　　　 00000018      (Error count is "0x18" ( 4 + 4*2 + 4*3(for third error) =  24 ))

    EMIF1_EMIF_1B_ECC_ERR_THRSH               　　　　00000000

    EMIF1_EMIF_1B_ECC_ERR_DIST_1                     　42010000      (error bit is overlayed)

    EMIF1_EMIF_1B_ECC_ERR_ADDR_LOG                   00000070

    EMIF1_EMIF_2B_ECC_ERR_ADDR_LOG                   00000000

     

    9．Repeat 4 - 8 Bit change @0x8000000F　

    0x80000000   00000001      00000002      00000004     00000000

    0x80000010   00000010      00000020      00000040      00000080

    0x80000020   00000100      00000200      00000400      00000800

    0x80000030   00001000      00002000      00004000      00008000

    0x80000040   00000000     00020000      00040000      00080000

    0x80000050   00100000      00200000      00400000      00800000

    0x80000060   01000000     00000000     04000000      08000000

    0x80000070   10000000      20000000     00000000     80000000

     

    EMIF1_EMIF_ECC_CTRL_REG                         　C0000003

    EMIF1_EMIF_ECC_ADDRESS_RANGE_1                   00010000

    EMIF1_EMIF_ECC_ADDRESS_RANGE_2                   00020001

    EMIF1_EMIF_READ_WRITE_EXECUTION_THRESHOLD 　00000305

    EMIF1_EMIF_COS_CONFIG                           　00FFFFFF

    EMIF1_EMIF_1B_ECC_ERR_CNT                 　　　　00000028     (Error count is "0x28" (4+4*2+4*3+4*4(for fourth error) = 40))

    EMIF1_EMIF_1B_ECC_ERR_THRSH               　　　　00000000

    EMIF1_EMIF_1B_ECC_ERR_DIST_1                     　42010008      (error bit is overlayed)

    EMIF1_EMIF_1B_ECC_ERR_ADDR_LOG                   00000070

    EMIF1_EMIF_2B_ECC_ERR_ADDR_LOG                   00000000

     

    10．Read FIFO's data out by writing "1" in EMIF1_EMIF_1B_ECC_ERR_ADDR_LOG register. four fifo's data are same.

    It is 0x8000007x.

    00000070

    00000070

    00000070

    00000070

    00000000

     

     

    * Confirmation results of ECC 2B error :

    Procedure and results

     

    1．Memory initialization same as 1bit error

    0x80000000   00000001      00000002      00000004      00000008

    0x80000010   00000010      00000020      00000040      00000080

    0x80000020   00000100      00000200      00000400      00000800

    0x80000030   00001000      00002000      00004000      00008000

    0x80000040   00010000      00020000      00040000      00080000

    0x80000050   00100000      00200000      00400000      00800000

    0x80000060   01000000      02000000      04000000      08000000

    0x80000070   10000000      20000000      40000000      80000000

     

    2．ECC Disable, and Bit change @0x8000003C

    0x80000000   00000001      00000002      00000004      00000000

    0x80000010   00000010      00000020      00000040      00000040

    0x80000020  00000100      00000200      00000400      00000800

    0x80000030   00001000      00002000      00004000      00008000

    0x80000040   00000000      00020000      00040000      00080000

    0x80000050   00100000      00200000      00000000      00800000

    0x80000060   01000000      00000000      04000000      08000000

    0x80000070   10000000      20000000      00000000     10000000

     

    3．ECC enable

    0x80000000   00000001      00000002      00000004      00000008

    0x80000010   00000000      00000000      00000000      00000000

    0x80000020   00000100      00000200      00000400      00000800

    0x80000030   00001000      00002000      00004000      00008000

    0x80000040   00010000      00020000      00040000      00080000

    0x80000050   00100000      00200000      00400000      00800000

    0x80000060   01000000      02000000      04000000      08000000

    0x80000070   00000000     00000000      00000000      00000000　 (whole 128bit line that 2bit error happened is "0".)

     

    4．Confirmed registers

    EMIF1_EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS       00000010 (2bit error interrupt)

    EMIF1_EMIF_SYSTEM_OCP_INTERRUPT_STATUS             00000000

    EMIF1_EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET       00000000

    EMIF1_EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR   00000000

    EMIF1_EMIF_ECC_CTRL_REG                                 C0000003

    EMIF1_EMIF_ECC_ADDRESS_RANGE_1                       00000000

    EMIF1_EMIF_ECC_ADDRESS_RANGE_2                       00010001

    EMIF1_EMIF_READ_WRITE_EXECUTION_THRESHOLD       00000305

    EMIF1_EMIF_COS_CONFIG                                   00FFFFFF

    EMIF1_EMIF_1B_ECC_ERR_CNT                              00000000

    EMIF1_EMIF_1B_ECC_ERR_THRSH                           00000000

    EMIF1_EMIF_1B_ECC_ERR_DIST_1                           00000000

    EMIF1_EMIF_1B_ECC_ERR_ADDR_LOG                      00000000

    EMIF1_EMIF_2B_ECC_ERR_ADDR_LOG                       00001070 (2bit error happened at 0x8000107x)

     

     

    I appreciate your quick reply.

     

    Best regards,

    Michi

     

  • 0
    TI__Guru**** 393215 points
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