AM335x + Beaglebone Black - mcasp0_ahclkx - MCLK

Bruce Glazier

Other Parts Discussed in Thread: TLV320AIC3104

I need help understanding MCLK for my application with the Beaglebone Black (Rev C) because currently I am not seeing any oscillation at GPIO3_21 (P9.25).

In the above diagram, Y4 the oscillator, is connected to GPMC_A11 at PIN 1 (OE) and on GPIO3_21 (mcasp0_ahclk).
I've been trying to determine how these PINS should be defined for proper operation of the oscillator and I'm not getting anywhere.

I am attempting to use mcasp0_ahclk or P9.25 was MCLK for mcasp1 as seen here:

fragment@1 {
		target = <&am33xx_pinmux>;
		__overlay__ {
				mcasp1_pins: mcasp1_pins {
				pinctrl-single,pins = <
					0x1AC 0x00	 	/* mcasp0_ahclkx,  P9_25 */
					0x144 0x24 		/* mcasp1_axr3, P9_16, MODE 4  */
					0x1A8 0x23	    /*mcasp1_axr0, P9_41, MODE 3  */
					0x1A4 0x23  	/*mcasp1_fsx, P9.27, MODE 3 */
					0x1A0 0x23	/*mcasp1_aclkx,P9.42, MODE 3 */
						/* 0x6c  0x07	GPMC_A11  */
				>;
				};

I'm not sure how 0x1ac should be defined as I've seen it defined as an output, 0x00, for the working AudioCape_RevB dts from CircuitCo as well as an input on other discussions. I found that within the main am335x-boneblack.dts mcasp0 has pincltr,single = <0x6c 0x7> as one of the options which the GPMC_A11 pin V17 and 0x7 configures it for GPIO1_27, output. So if both pins attached to the oscillator are setup as outputs then how does this work? If someone can provide some insight/explanations on how to accomplish this task I would greatly appreciate it.

FYI- The codec I am using is a tlv320aic3104, kernel is 4.1-ti-r35.

Thank you,

Bruce

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

You are referring to a diagram, but no diagram can be seen on your post.

0 Bruce Glazier over 9 years ago in reply to Biser Gatchev-XID

Prodigy 50 points

Strange, the diagram was there when I created the post. This is the diagram I meant.

Found a link that could answer my question: https://groups.google.com/forum/m/#!topic/beagleboard/0SOAheyjTnw

This confirms that GPIO1_27 should be configured as an output that can enable/disable the oscillator. Meanwhile P9.25 should be configured as an input. May have to remove all references to 0x06C from device tree. I will try on Monday and report back, meanwhile if anyone can confirm this, that would be great.

Thanks,

Bruce

0 Biser Gatchev-XID over 9 years ago in reply to Bruce Glazier

TI__Guru**** 393215 points

Bruce Glazier said:
This confirms that GPIO1_27 should be configured as an output that can enable/disable the oscillator. Meanwhile P9.25 should be configured as an input

Correct, with the addition that GPIO3_21 must be pinmuxed to its McASP mode. GPIO1_27 should be pinmuxed to GPIO mode.

0 Bruce Glazier over 9 years ago in reply to Biser Gatchev-XID

Prodigy 50 points

Thanks Biser,

I'm not yet having any luck with configuring GPIO1_27 as a GPIO using the 'echo 59 > /sys/class/gpio/export' command as I am getting a "Device Busy or Not Ready" error. I removed reference of 0x06C from the main .dtb under the MCASP0 sections BUT it just occurred to me as I write this that I have not defined the PINMODE for 0x06c afterwards. I've thought of simply adding 0x06C in GPIO mode to MCASP1 control pins but the end goal is to have both MCASP0 and MCASP1 share the same MCLK. For that reason I am thinking I can simply set GPIO1_27 high, unless I am mistaken with how that pin is used. Will continue my efforts and report back.

0 Bruce Glazier over 9 years ago in reply to Bruce Glazier

Prodigy 50 points

Still no luck, looks like I was going about this all wrong too. After decompiling my am335x-boneblack.dts, I found the following references:

		mcasp0_fck {
							#clock-cells = <0x0>;
							compatible = "fixed-factor-clock";
							clocks = <0x5>;
							clock-mult = <0x1>;
							clock-div = <0x1>;
							linux,phandle = <0x7f>;
							phandle = <0x7f>;
						};



	clk_mcasp0_fixed {
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
		clock-frequency = <0x1770000>;
		linux,phandle = <0x51>;
		phandle = <0x51>;
	};

	clk_mcasp0 {
		#clock-cells = <0x0>;
		compatible = "gpio-gate-clock";
		clocks = <0x51>;
		enable-gpios = <0x48 0x1b 0x0>;
		linux,phandle = <0x54>;
		phandle = <0x54>;
	};

I need to dig deeper into the gpio-gate-clock and determine how to use it for MCASP0 and MCASP1. I'm confused as to what these definitions are, why we need them all, and how they reference one another. I can see that many of the "fck" devices reference the same as the mcasp0_fck (clocks = <0x5>). I will keep digging but any hints or ideas are appreciated.

Thanks,

Bruce

0 Bruce Glazier over 9 years ago in reply to Bruce Glazier

Prodigy 50 points

Although I haven't completed my end goal, I have answered my own question. The gpio-gate-clock "clk_mcasp0" can be referenced by it's phandle 0x54. I modified my device tree overlay as follows:

sound_master:simple-audio-card,codec {
 sound-dai = <&tlv320aic3104_aq1>;
 /* system-clock-frequency = <12000000>; */
 clocks = <0x54>;
 };

Now when I do an arecord test.wav, I can see the clock present on P9.25 for MCASP1 and it no longer stalls. Now I see a buffer overflow issue but it is certainly an improvement.

Thanks,

Bruce

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AM335x + Beaglebone Black - mcasp0_ahclkx - MCLK