Other Parts Discussed in Thread: 66AK2H14
Hello.
I use a SRIO interface keystone2 system to FPGA. but Sometimes Error occurred.
DSP side is EVMK2h included 66AK2H14 rev 4.0 and used SYS/BIOS
FPGA side is Virtex 7 by Xilinx and IP core is SRIO Gen2 3.2 Rev 1.
Interface conditions are Lane Speed is 1.25G and Lane config is mode 4.
Purpose is Some data from FPGA to DSP DDR memory about 48KB every 200uS. bandwidth is about 2Gb.
When the transfer started, I checked packet number in DSP side. Transfer seems to fine.
about 10 min later, error has occurred about while 2~3 sec. I check the register address is 0x0290B158 (Port0 Error and Status CSR), value is 0x02030200 and I checkted input Ack ID using CSL_SRIO_GetACKStatus function input Ack ID is not changed.
Could I find another point to solve the problem??
Regards.
Shin.
