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OMAP-L138 DDR2 Configuration

Brad Griffis
Guru*** 125430 points

I'm looking at Section 2.13.2 "Initializing Following Device Power Up and Device RESET" in the DDR2 User's Guide.  Step 5 says to use PSC to put the DDR controller in synchReset state.  At what point do we re-enable?  Is it this same step or is it some time later?  I would assume that it should be right there, but didn't want to make a bad assumption.

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    TI__Expert 8785 points

    Brad,

    Based on the DDR initialization in the GEL files, you should do a PSC enable right after PSC sync reset.  I'll get this updated in the user guide.

    - Christina

  • 0 in reply to clam
    TI__Guru*** 125430 points

    Christina -- I have one other related question/clarification as you are doing this update.  I'm following the initialization procedure given in Section 2.13.2.  The last step in this section is to follow the instructions in 2.13.1.  Step 4 in 2.13.2 has me configure DRPYC1R.  As I continue I find myself configuring it once again in step 1 of 2.13.1.  Is it necessary to write this register twice?  If not, where is the correct place?

    FYI, let me help illustrate why this is important.  Let's say you decide to use a different DDR speed.  Based on speed your CAS latency may change.  Since CAS latency changes now "read latency" (RL) changes (i.e. CAS+1).  So to change the CAS latency I need to remember to update SDCR and DRPYC1R twice.  Just seems like it could be an easy place for mistakes so it would be good to clean this up if possible.

    Thanks!