How to use MIcrel KSZ9031 with MDIO and CPSW into the AM3352 ?

I am using the TI-SDK processor 2.0 - Arago

Hi,

Try using the default dts nodes (refer to am335x-evmsk.dts:

&mac {

    pinctrl-names = "default", "sleep";

    pinctrl-0 = <&cpsw_default>;

    pinctrl-1 = <&cpsw_sleep>;

    dual_emac = <1>;

    status = "okay";

};

&davinci_mdio {

     pinctrl-names = "default", "sleep";

     pinctrl-0 = <&davinci_mdio_default>;

     pinctrl-1 = <&davinci_mdio_sleep>;

     status = "okay";

};

&cpsw_emac0 {

      phy_id = <&davinci_mdio>, <0>;

      phy-mode = "rgmii-txid";

      dual_emac_res_vlan = <1>;

};

I don't think you need the skew parameters in your dts. However, if you wish to explicitly specify the skew in your dts, have a look at Documentation/devicetree/bindings/mikrel-ksz90x1.txt for guidance on how to do it. 

Additionally you must enable the MIKREL PHY support either in tisdk_am335x-evm_defconfig, or through menuconfig.

Best Regards, 
Yordan

Hi, 

SHmuel Weiss said:

Now, I am seeing the Kernel saying:

[ 1.576184] Micrel KSZ9031 Gigabit PHY 4a101000.mdio:00: no of_node; not parsing pinctrl DT
[ 1.576874] Micrel KSZ9031 Gigabit PHY 4a101000.mdio:01: no of_node; not parsing pinctrl DT
[ 1.580960] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver Micrel KSZ9031 Gigabit PHY
[ 1.590814] davinci_mdio 4a101000.mdio: phy[1]: device 4a101000.mdio:01, driver Micrel KSZ9031 Gigabit PHY

Why I am getting "not parsing pinctrl DT" ?

The "no of_nod; not parsing pinctrl DT" is a debug message from devicetree.c driver, specifically the following fragment: 

/* CONFIG_OF enabled, p->dev not instantiated from DT */
if (!np) {
         if (of_have_populated_dt())
                            dev_dbg(p->dev,
                                           "no of_node; not parsing pinctrl DT\n");
         return 0;
}

As you can see this is a debug message, not an error message. You can see from the kernel log that the phy is actually detected: 
[ 1.580960] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver Micrel KSZ9031 Gigabit PHY
[ 1.590814] davinci_mdio 4a101000.mdio: phy[1]: device 4a101000.mdio:01, driver Micrel KSZ9031 Gigabit PHY

1. Can you share the pinmux settings for MDIO & CPSW? Can you verify that you do not mux these pins in other dts node? 

2. 

SHmuel Weiss said:

why Link detected is NO ?

This may be because your network interface is down. Before checking if the network cable is connected (with ethtool eth0), you need to enable the interface with ifconfig or ifup. Can you share the output of ifup eth0 or ifcofnig eth0 up? 

Best Regards, 

Yordan

FYI - the whole file below and the output of the ifup (with some debug info I added to the micrel.c) :

root@am335x-evm:~# ifup eth0
[   73.572536] net eth0: initializing cpsw version 1.12 (0)
[   73.653098] WARNING: ksz9031_config_init is called !!
[   73.658218] WARNING: SKEW IS identified !!
[   73.662361] WARNING:  ksz9031_of_load_skew_values inumfields: 2 reg:08  matches:0 of_node name:mdio type:<NULL> field:rxc-skew-ps!!
[   73.675155] WARNING:  ksz9031_of_load_skew_values inumfields: 2 reg:08  matches:1 of_node name:mdio type:<NULL> field:txc-skew-ps!!
[   73.687139] WARNING: SKEW write to reg: 8 value:953
[   73.692656] WARNING:  ksz9031_of_load_skew_values inumfields: 2 reg:04  matches:0 of_node name:mdio type:<NULL> field:txen-skew-ps!!
[   73.705338] WARNING:  ksz9031_of_load_skew_values inumfields: 2 reg:04  matches:1 of_node name:mdio type:<NULL> field:rxdv-skew-ps!!
[   73.717861] WARNING: SKEW write to reg: 4 value:113
[   73.723981] WARNING:  ksz9031_of_load_skew_values inumfields: 4 reg:05  matches:0 of_node name:mdio type:<NULL> field:rxd0-skew-ps!!
[   73.735994] WARNING:  ksz9031_of_load_skew_values inumfields: 4 reg:05  matches:1 of_node name:mdio type:<NULL> field:rxd1-skew-ps!!
[   73.748189] WARNING:  ksz9031_of_load_skew_values inumfields: 4 reg:05  matches:2 of_node name:mdio type:<NULL> field:rxd2-skew-ps!!
[   73.760181] WARNING:  ksz9031_of_load_skew_values inumfields: 4 reg:05  matches:3 of_node name:mdio type:<NULL> field:rxd3-skew-ps!!
[   73.772348] WARNING: SKEW write to reg: 5 value:30583
[   73.778056] WARNING:  ksz9031_of_load_skew_values inumfields: 4 reg:06  matches:0 of_node name:mdio type:<NULL> field:txd0-skew-ps!!
[   73.790215] WARNING:  ksz9031_of_load_skew_values inumfields: 4 reg:06  matches:1 of_node name:mdio type:<NULL> field:txd1-skew-ps!!
[   73.802206] WARNING:  ksz9031_of_load_skew_values inumfields: 4 reg:06  matches:2 of_node name:mdio type:<NULL> field:txd2-skew-ps!!
[   73.814372] WARNING:  ksz9031_of_load_skew_values inumfields: 4 reg:06  matches:3 of_node name:mdio type:<NULL> field:txd3-skew-ps!!
[   73.826358] WARNING: SKEW write to reg: 6 value:4369
[   73.832212] net eth0: phy found : id is : 0x221622
[   73.839957] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
udhcpc (v1.23.1) started
Sending discover...
Sending discover...
Sending discover...
No lease, forking to background

========================================== DTS========================================

&mac {
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&cpsw_default>;
    pinctrl-1 = <&cpsw_sleep>;
    dual_emac = <1>;
    status = "okay";
};

&davinci_mdio {
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&davinci_mdio_default>;
    pinctrl-1 = <&davinci_mdio_sleep>;
    status = "okay";
/*Configuration of the MICREL */
    rxdv-skew-ps = <420>;/*0    =>    0+420 = 420 */
    txen-skew-ps = <60>; /*-360 => -360+420 = 60*/

    rxd0-skew-ps = <420>;/*0    =>    0+420 = 420 */
    rxd1-skew-ps = <420>;/*0    =>    0+420 = 420 */
    rxd2-skew-ps = <420>;/*0    =>    0+420 = 420 */
    rxd3-skew-ps = <420>;/*0    =>    0+420 = 420 */

    txd0-skew-ps = <60>;/*-360 => -360+420 = 60*/
    txd1-skew-ps = <60>;/*-360 => -360+420 = 60*/
    txd2-skew-ps = <60>;/*-360 => -360+420 = 60*/
    txd3-skew-ps = <60>;/*-360 => -360+420 = 60*/

    txc-skew-ps = <1740>;/*840 =>  840+900 = 1740*/
    rxc-skew-ps = <1500>;/*600 =>  600+900 = 1500*/
};

&cpsw_emac0 {
    phy_id = <&davinci_mdio>, <0>;
    phy-mode = "rgmii-txid";
    dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
    phy_id = <&davinci_mdio>, <1>;
    phy-mode = "rgmii-txid";
    dual_emac_res_vlan = <2>;
};

Thanks for your help

IN the meantime I managed myself to debug my issues using u-boot

I patched manually the micrel.c file and the board.c to confgiure some stuff: Now I am getting:

MDIO check and SKEW setup

U-Boot# mdio list
cpsw:
0 - Micrel ksz9031 <--> cpsw

Read the SKEW registers first:
mdio rx cpsw 2.4
mdio rx cpsw 2.5
mdio rx cpsw 2.6
mdio rx cpsw 2.8
mdio wx cpsw 2.4 0x0071
mdio wx cpsw 2.5 0x7777
mdio wx cpsw 2.6 0x1111
mdio wx cpsw 2.8 0x0379

My issue now is with the LINK signal, why it is always 0 and why the auto-negotiation is failing....

U-Boot# mii dump 0 1
1.     (7949)                 -- PHY status register --
  (8000:0000) 1.15    =     0    100BASE-T4 able
  (4000:4000) 1.14    =     1    100BASE-X  full duplex able
  (2000:2000) 1.13    =     1    100BASE-X  half duplex able
  (1000:1000) 1.12    =     1    10 Mbps    full duplex able
  (0800:0800) 1.11    =     1    10 Mbps    half duplex able
  (0400:0000) 1.10    =     0    100BASE-T2 full duplex able
  (0200:0000) 1. 9    =     0    100BASE-T2 half duplex able
  (0100:0100) 1. 8    =     1    extended status
  (0080:0000) 1. 7    =     0    (reserved)
  (0040:0040) 1. 6    =     1    MF preamble suppression
  (0020:0000) 1. 5    =     0    A/N complete
  (0010:0000) 1. 4    =     0    remote fault
  (0008:0008) 1. 3    =     1    A/N able
  (0004:0000) 1. 2    =     0    link status
  (0002:0000) 1. 1    =     0    jabber detect
  (0001:0001) 1. 0    =     1    extended capabilities


U-Boot# setenv ipaddr 192.168.0.250
U-Boot# ping 192.168.0.91
cpsw Waiting for PHY auto negotiation to complete......... TIMEOUT !
Using cpsw device
ping failed; host 192.168.0.91 is not alive

Hello,

Could you tell me what is connected to the physical Ethernet port? The auto-negotiation is autonomously handled by the PHY(s) when enabled, so the CPSW doesn't really have any part in the negotiation process itself. The MDIO interface will poll the PHY looking for status bit updates (including negotiation complete and link up) and then update the CPSW registers with the results.

Also,

I note that the driver is setting the Micrel internal skews...have you verified that the values are correct? This data would be obtained via a setup/hold timing analysis of the MAC-PHY interface on your particular board. This wouldn't affect the auto-negotiation issue, but it would affect actual data transfer once the link is up.

U-Boot# mdio rx cpsw 2.4
Reading from bus cpsw
PHY at address 0:
2.4 - 0x71
U-Boot# mdio rx cpsw 2.5
Reading from bus cpsw
PHY at address 0:
2.5 - 0x7777
U-Boot# mdio rx cpsw 2.6
Reading from bus cpsw
PHY at address 0:
2.6 - 0x1111
U-Boot# mdio rx cpsw 2.8
Reading from bus cpsw
PHY at address 0:
2.8 - 0x379

We have Micrel 9031 PHY, the Ethernet port is connected to a little switch, on it we can see a led ON saying this a 1GBps port. (we used different RJ45 to be sure it's not an issue in the network).

We are reading the register 0x1 from the PHY and the Link bit is 0 always.

the SKEWS are well configured.

We are now debugging this from u-boot directly as reported above.

What could interfere between the CPU/PHY in that case preventing the PHY register to be updated and reflecting the real LINK status. BTW the led on the ethernet port are also blinking (the left one is blinking and the right one is OFF).

The SKEW are correct (based on what our Hardware engineer told us to set there)

U-Boot# mii dump 0 5
5.     (0000)                 -- Autonegotiation partner abilities register --
  (8000:0000) 5.15    =     0    next page able
  (4000:0000) 5.14    =     0    acknowledge
  (2000:0000) 5.13    =     0    remote fault
  (1000:0000) 5.12    =     0    (reserved)
  (0800:0000) 5.11    =     0    asymmetric pause able
  (0400:0000) 5.10    =     0    pause able
  (0200:0000) 5. 9    =     0    100BASE-T4 able
  (0100:0000) 5. 8    =     0    100BASE-X full duplex able
  (0080:0000) 5. 7    =     0    100BASE-TX able
  (0040:0000) 5. 6    =     0    10BASE-T full duplex able
  (0020:0000) 5. 5    =     0    10BASE-T able
  (001f:0000) 5. 4- 0 =     0    selector = ???

Hi SHmuel,

- How have you assessed that the RGMII HW design is working? What type of signal integrity tests have you done?
Note that the Sitara AM4378 GP EVM and AM4378 Starterkit do use the KSZ9031RN PHY. It might be a good comparaison point.

Also in term of SW the AM437x Linux SDK 1.02 is available so you could have a look if there are KSZ9031RN specific add-on code in the kernel drivers.
For SDK and EVM docs see:
http://www.ti.com/product/AM4378/toolssoftware


Note that AM437x CSPW has some improvements compared to the AM335x CPSW but the difference for you use case might not be that significant.See  page 11 and 12 of sitara_boot_camp_12_am437x__technical_overview.pptx

at https://training.ti.com/sitara%E2%84%A2-arm%C2%AE-processors-boot-camp-am437x-technical-overview

Anthony

Your register dump shows that the link partner isn't advertising any capabilities...there is nothing for the MAC to auto-negotiate with.
Can you verify that both clocks (TXCLK and RXCLK) are active?

Use an o-scope to measure the  RX CLK from the PHY.

Have you addressed the issue with your link partner? Either you are reading the wrong PHY, or whatever you are connected to via Ethernet is not configured correctly.

My issue with my Link partner is related to the clock I think.

I am not seeing LINK-UP, neither link partner info, so my RX configuration seems to be weird.

Below the pinmux configuration: where Clock is defined ? is it the cpsw_cpts_rft_clk ? Our HW engineer told me that he see 125Mhz on TX but not on RX. can you please point me to the right place to configure this ? thanks.

 mac: ethernet@4a100000 {
            compatible = "ti,am335x-cpsw","ti,cpsw";
            ti,hwmods = "cpgmac0";
            clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
            clock-names = "fck", "cpts";
            cpdma_channels = <8>;
            ale_entries = <1024>;
            bd_ram_size = <0x2000>;
            no_bd_ram = <0>;
            rx_descs = <64>;
            mac_control = <0x20>;
            slaves = <2>;
            active_slave = <0>;
            cpts_clock_mult = <0x80000000>;
            cpts_clock_shift = <29>;
            reg = <0x4a100000 0x800
                   0x4a101200 0x100>;
            #address-cells = <1>;
            #size-cells = <1>;
            interrupt-parent = <&intc>;
            /*
             * c0_rx_thresh_pend
             * c0_rx_pend
             * c0_tx_pend
             * c0_misc_pend
             */
            interrupts = <40 41 42 43>;
            ranges;
            syscon = <&scm_conf>;
            status = "disabled";

            davinci_mdio: mdio@4a101000 {
                compatible = "ti,davinci_mdio";
                #address-cells = <1>;
                #size-cells = <0>;
                ti,hwmods = "davinci_mdio";
                bus_freq = <1000000>;
                reg = <0x4a101000 0x100>;
                status = "disabled";
            };

            cpsw_emac0: slave@4a100200 {
                /* Filled in by U-Boot */
                mac-address = [ 00 00 00 00 00 00 ];
            };

            cpsw_emac1: slave@4a100300 {
                /* Filled in by U-Boot */
                mac-address = [ 00 00 00 00 00 00 ];
            };

            phy_sel: cpsw-phy-sel@44e10650 {
                compatible = "ti,am3352-cpsw-phy-sel";
                reg= <0x44e10650 0x4>;
                reg-names = "gmii-sel";
            };

cpsw_default: cpsw_default {
        pinctrl-single,pins = <
            /* Slave 1 */
            0x12c (PIN_OUTPUT | MUX_MODE2)  /* mii1_txclk.rmii1_tclk */
            0x114 (PIN_OUTPUT | MUX_MODE2)  /* mii1_txen.rgmii1_tctl */
            0x128 (PIN_OUTPUT | MUX_MODE2)  /* mii1_txd0.rgmii1_td0 */
            0x124 (PIN_OUTPUT | MUX_MODE2)  /* mii1_txd1.rgmii1_td1 */
            0x120 (PIN_OUTPUT | MUX_MODE2)  /* mii1_txd0.rgmii1_td2 */
            0x11c (PIN_OUTPUT | MUX_MODE2)  /* mii1_txd1.rgmii1_td3 */
            0x130 (PIN_INPUT | MUX_MODE2)   /* mii1_rxclk.rmii1_rclk */
            0x118 (PIN_INPUT | MUX_MODE2)   /* mii1_rxdv.rgmii1_rctl */
            0x140 (PIN_INPUT | MUX_MODE2)   /* mii1_rxd0.rgmii1_rd0 */
            0x13c (PIN_INPUT | MUX_MODE2)   /* mii1_rxd1.rgmii1_rd1 */
            0x138 (PIN_INPUT | MUX_MODE2)   /* mii1_rxd0.rgmii1_rd2 */
            0x134 (PIN_INPUT | MUX_MODE2)   /* mii1_rxd1.rgmii1_rd3 */

            /* Slave 2 */
            0x58 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a6.rgmii2_tclk */
            0x40 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a0.rgmii2_tctl */
            0x54 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a5.rgmii2_td0 */
            0x50 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a4.rgmii2_td1 */
            0x4c (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a3.rgmii2_td2 */
            0x48 (PIN_OUTPUT | MUX_MODE2)   /* gpmc_a2.rgmii2_td3 */
            0x5c (PIN_INPUT | MUX_MODE2)    /* gpmc_a7.rgmii2_rclk */
            0x44 (PIN_INPUT | MUX_MODE2)    /* gpmc_a1.rgmii2_rtcl */
            0x6c (PIN_INPUT | MUX_MODE2)    /* gpmc_a11.rgmii2_rd0 */
            0x68 (PIN_INPUT | MUX_MODE2)    /* gpmc_a10.rgmii2_rd1 */
            0x64 (PIN_INPUT | MUX_MODE2)    /* gpmc_a9.rgmii2_rd2 */
            0x60 (PIN_INPUT | MUX_MODE2)    /* gpmc_a8.rgmii2_rd3 */
            
        >;
    };
    cpsw_sleep: cpsw_sleep {
        pinctrl-single,pins = <
            /* Slave 1 reset value */
            0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)

            /* Slave 2 reset value */
            0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
            0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
        >;
    };

&mac {
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&cpsw_default>;
    pinctrl-1 = <&cpsw_sleep>;
    dual_emac = <1>;
    status = "okay";
};

&davinci_mdio {
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&davinci_mdio_default>;
    pinctrl-1 = <&davinci_mdio_sleep>;
    status = "okay";
/*Configuration of the MICREL */
    rxdv-skew-ps = <420>;/*0    =>    0+420 = 420 */
    txen-skew-ps = <60>; /*-360 => -360+420 = 60*/

    rxd0-skew-ps = <420>;/*0    =>    0+420 = 420 */
    rxd1-skew-ps = <420>;/*0    =>    0+420 = 420 */
    rxd2-skew-ps = <420>;/*0    =>    0+420 = 420 */
    rxd3-skew-ps = <420>;/*0    =>    0+420 = 420 */

    txd0-skew-ps = <60>;/*-360 => -360+420 = 60*/
    txd1-skew-ps = <60>;/*-360 => -360+420 = 60*/
    txd2-skew-ps = <60>;/*-360 => -360+420 = 60*/
    txd3-skew-ps = <60>;/*-360 => -360+420 = 60*/

    txc-skew-ps = <1740>;/*840 =>  840+900 = 1740*/
    rxc-skew-ps = <1500>;/*600 =>  600+900 = 1500*/
};

&cpsw_emac0 {
    phy_id = <&davinci_mdio>, <0>;
    phy-mode = "rgmii";
    dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
    phy_id = <&davinci_mdio>, <1>;
    phy-mode = "rgmii";
    dual_emac_res_vlan = <2>;
};

Below the dmesg file and the schematics of the board + DTS we are using.

Be careful, the DTS attached is the DTS we use when PHY is configured with address 0x00.

The dmesg file is the boot log when we use PHY with addr 0x02. (Not really different except this line)

[    1.584606] davinci_mdio 4a101000.mdio: phy[2]: device 4a101000.mdio:02, driver Micrel KSZ9031 Gigabit PHY

---- FILES removed due to legacy issue ----

Our Product is based on the architecture of AM335x-EVM-SK - we use am335x-evm-02.00.00.00