on 6455 srio

Travis,

        Thank you for your reply. I have pass the test.

       Do you have  example project  on bring  up a rapidio  system with tsi578 swtich and other pe?

Great!

We do not really have any projects with non-TI processing elements, but if you are working with the TSI578, you can probably get some initialization/bringup info from IDT.  Once this is configured, there really is no difference from the loopback example.

Regards,

Travis

 I have another problem!

The externl loop-back program traps into a while loop,where the status of srio is port uninitialized.

what may cause the problem?

Hi Dong,

Usually, when the port_ok bit is not being set, it means one of two things, either the link partners PLLs aren't setup correctly and they are operating at different data rates, or, their port widths are incompatible somehow.  Since this is loopback, neither of these should be occurring.  It has to be a physical connection issue with the loopback, or a setup issue.  Is boot_complete being written in your example?

Regards,

Travis

yes the boot_complete is written as 1.

i will check the pll and the width also.

The register read out as follows:

per_set_cntl=0x05000360

serdes_cfg0_cntl=0x0000000b;

sp0_ctl=0x5168000d;

sp_ip_mode=0x4000002a;

And I want to set the port as 1p/1x on port0.

what is wrong?

Not completely sure, but I think it has to do with the port width and/or setup. How are you doing loopback?  You are doing loopback with external cables correct?

If you want single port, that can be a 1x (using lane 0 or lane 2, and port 0) or 4x (using all lanes and port 0), then you must have: SP_IP_MODE[31:30]=0b00 and PER_SET_CNTL[8]=0b0

If you want four port mode (each port 1x, using its own lane and port #) then: SP_IP_MODE[31:30]=0b01 and PER_SET_CNTL[8]=0b1.  This is the mode you have selected, and is what I'd suggest you get working first.

You have SP(0)_CTL bit 24 set, which is a reserved setting, use [26:24]=0b000.  Bits [31:30] are 0b01, which indicates single 1x/4X port might just reflect the default value, but I'm unsure why bits[29:27=0b010 indicating four lane port.  Even if the port isn't initialized, these bits shouldn't read this I don't think.

Here is a snapshot of all the registers that the SRIO bootrom parameter table configure for the C6455.  These are the minimum registers that should be touched, all others, the default values can be used and reconfigured later.  The sequence is important, with boot_complete being set at the end....

SRIO  boot Config 0 - 4 ports 1x mode, 125Mhz reference, 1.25Gbps